Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2002-11-05
2004-08-10
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C435S166000, C435S149000, C435S151000, C435S155000
Reexamination Certificate
active
06773944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a thin film transistor (hereinafter referred to as TFT) with a GOLD (abbreviated form of “gate-overlapped-LDD”) structure and a method of manufacturing the same. Note that the semiconductor device in this specification indicates semiconductor devices in general the circuit of which is configured by semiconductor devices including a TFT with a GOLD structure. For example, semiconductor display devices such as an active matrix liquid crystal display device and an organic EL (abbreviated form of “electro-luminescence”) display device are included in the category of the semiconductor device.
2. Description of the Related Art
In semiconductor display devices, such as an active matrix liquid crystal display device and an organic EL display device, the circuit of which is configured by TFTs on a transparent insulating substrate such as a glass substrate, a polycrystalline silicon TFT having a high field-effect mobility has attracted attention. A polycrystalline silicon film applied to the polycrystalline silicon TFT has a higher field-effect mobility of an electron or hole than a conventional amorphous silicon film, and thus has an advantage that integration of not only a pixel transistor but also a driver circuit as a peripheral circuit can be realized. Therefore, each company has been advancing the development of an active matrix semiconductor display device the circuit of which is configured by polycrystalline silicon TFTs.
In the polycrystalline silicon TFT, it has a high field-effect mobility, but on the other hand, there is observed deterioration phenomena such as lowering of the field-effect mobility or an ON current (current that flows in an ON state) and increase in an OFF current (current that flows in an OFF state) when the polycrystalline silicon TFT is continuously driven. These have been problems in terms of reliability. The deterioration phenomenon is called a hot carrier phenomenon, and is known to be caused by hot carriers generated due to a high electric field in the vicinity of a drain.
The hot carrier phenomenon is one first discovered in a MOS (abbreviated form of “metal oxide semiconductor”) transistor which is manufactured on a semiconductor substrate, and it has been found that the cause of the phenomenon is the high electric field in the vicinity of a drain. Various basic examinations have been made for measures against hot carriers. The MOS transistor with a design rule of 1.5 &mgr;m or less adopts an LDD (abbreviated form of “lightly doped drain”) structure. In the LDD structure, an n-type or p-type low concentration impurity region (n
−
region or p
−
region) is formed in a drain end portion by utilizing a gate side wall that is comprised of an insulating film, and a gradient is imparted to an impurity concentration of a drain junction, thereby relaxing an electric field concentration in the vicinity of a drain. Here, an n-type low concentration impurity region and an n-type high concentration impurity region are respectively called an n
−
region and an n
+
region, and a p-type low concentration impurity region and a p-type high concentration impurity region are respectively called a p
−
region and a p
+
region.
However, in the LDD structure, the resistance of the low concentration impurity region (n
−
region or p
−
region) is large while a drain withstand voltage is improved much compared with a single drain structure. Thus, the LDD structure has a defect that a drain current decreases. Further, there has been the problem of a deterioration mode peculiar to the LDD in which: a high electric field region exists just under the side wall; impact ionization becomes maximum there; hot electrons are implanted into the side wall; and thus, the low concentration impurity region (n
−
region or p
−
region) is depleted, and the resistance is further increased. The above-mentioned problem has been tangible along with the reduction of a channel length. Thus, as to the MOS transistor with a design rule of 0.5 &mgr;m or less, the GOLD structure is developed in which a low concentration impurity region (n
−
region or p
−
region) is formed so as to overlap with an end portion of a gate electrode as a structure for overcoming the above-mentioned problem, and the application of the structure to mass production has been advancing.
Under the above-mentioned background, as to the polycrystalline silicon TFT manufactured on a transparent insulating substrate such as a glass substrate as well, the development of the LDD structure or GOLD structure has been progressing with the purpose of relaxing a high electric field in the vicinity of a drain, similar to the MOS transistor. The LDD structure is such that an n-type or p-type low concentration impurity region (n
−
region or p
−
region) that functions as an electric field relaxation region is formed in a semiconductor layer comprised of a polycrystalline silicon film corresponding to the outside of a gate electrode, and a high concentration impurity region (n
+
region or p
+
region) with the same conductivity as a source region or drain region is formed outside thereof. The LDD structure concerned has an advantage that an OFF current is small and a disadvantage that a hot carrier suppression effect due to relaxation of an electric field in the vicinity of a drain is small. On the other hand, in the GOLD structure, a low concentration impurity region (n
−
region or p
−
region) is formed so as to overlap with an end portion of a gate electrode. Thus, the GOLD structure has an advantage that a hot carrier suppression effect is large and a disadvantage that an OFF current increases, in comparison with the LDD structure.
As described above, each of the LDD structure and the GOLD structure has good points and bad points. Thus, in the actual semiconductor display device, from the viewpoint of quality improvement of the semiconductor display device, there is examined the effective combination in circuit configuration of a low OFF current characteristic of the LDD structure and a high hot carrier resistance of the GOLD structure. Specifically, in the case of a pixel TFT in a pixel region, the gate structure is preferable in which importance is placed on reduction in an OFF current value rather than high reliability to a hot carrier, and thus, the LDD structure having a low OFF current characteristic is suitable. On the other hand, in the case of a peripheral circuit consisting of a driver circuit, the gate structure is preferable in which importance is placed on high reliability to a hot carrier rather than a low OFF current characteristic, and thus, the GOLD structure having high hot carrier resistance is suitable. Therefore, the recent semiconductor display device the circuit of which is configured by a polycrystalline silicon TFT has a tendency that a pixel TFT in a pixel region is comprised of an LDD structure TFT, and a peripheral circuit is comprised of a GOLD structure TFT.
Note that, as to a known example on an n-channel polycrystalline silicon GOLD structure TFT, the structure and basic characteristics of the n-channel GOLD structure TFT are disclosed in Mutsuko Hatano, Hajime Akimoto, and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997. In the structure of the GOLD structure TFT examined here, a gate electrode and a side wall for LDD are formed of polycrystalline silicon, an n-type low concentration impurity region (n
−
region) that functions as an electric filed relaxation region is formed in an active layer (formed of polycrystalline silicon) just under the side wall for LDD, and a high concentration impurity region (n
+
region) with the same conductivity which functions as a source region or drain region is formed outside thereof. As to the basic characteristics, a large drain current is obtained together with relaxatio
Fish & Richardson P.C.
Lebentritt Michael
Semiconductor Energy Laboratory Co,. Ltd.
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