Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-05-23
2004-06-29
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S632000, C257S759000, C257S760000
Reexamination Certificate
active
06756676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device which contains a plurality of wirings juxtaposed with one another and uses SiOF as an insulating film, a semiconductor device having multilayer metallization and uses SiOF as an interlayer insulating film, and a method of manufacturing these semiconductor devices.
2. Description of the Related Art
Following the enhancement in integration degree and micro-structure design of semiconductor devices, there have been tendencies to reduce the wiring pitch and increase the parasitic capacitance (called as “wiring capacitance”) attendant to wirings. Materials having lower specific dielectric constant have been used as interlayer insulating films to reduce the wiring capacitance. Of these materials, SiOF is an insulating material having the lowest specific dielectric constant in inorganic materials formable by a plasma CVD method which has been hitherto used.
A semiconductor device using SiOF as an interlayer insulating film will be described with reference to FIG.
1
and
FIGS. 2
to
4
.
FIG. 1
is a cross-sectional view showing a conventional semiconductor device, and
FIGS. 2
to
4
are cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG.
1
. In this case, a three-layer metallization structure is shown. As shown in
FIG. 1
, an interlayer insulating film
12
formed of SiOF is provided in a wire gap portion of a first layer wiring
8
and at the upper side of the first layer wiring
8
, and also an interlayer insulating film
17
formed of SiOF is provided in a wire gap portion of a second layer wiring
15
and at the upper side of the second layer wiring
15
. The thickness of the interlayer insulating film
17
is set to 0.6 micrometer to 1.0 micrometer at the upper side of the second layer wiring
15
.
A method of manufacturing such a conventional semiconductor device will be described with reference to
FIGS. 2
to
4
.
First, as shown in
FIG. 2
, a diffusion layer
1
and the element isolation region
2
are formed on the semiconductor substrate
3
, and the first interlayer insulating film
4
is grown on the diffusion layer
1
and the element isolation region
2
. Then a barrier metal layer
5
A, an aluminum layer
6
A and a titanium nitride layer
7
A are successively formed. Thereafter, a desired pattern is left to form the first layer wiring
8
, and SiOF film
11
is formed thereon.
Subsequently, as shown in
FIG. 3
, SiOF film
11
is flattened to form a flattened SiOF film
9
. Then, as shown in
FIG. 4
, a viahole
13
is selectively formed in the SiOF film
9
on the first layer wiring
8
to form a second interlayer insulating film
12
, a tungsten plug
14
is formed In the viahole
13
, and a barrier metal layer
5
B, an aluminum layer
6
B and a titanium nitride layer
7
B are successively formed. Thereafter, a desired pattern is left to form the second layer wiring
15
.
Subsequently, as shown in
FIG. 1
, a third interlayer insulating film
17
having a viahole
18
is formed, a tungsten plug
19
is formed in the viahole
18
, and a barrier metal layer
5
C, an aluminum layer
6
C and a titanium nitride layer
7
C are successively formed. Thereafter, a desired pattern is left to form the third layer wiring
20
. Then, a cover film
21
is formed, thereby completing the final structure shown in FIG.
1
.
In the semiconductor device thus constructed, when the fluorine concentration in SiOF constituting the interlayer insulating film is set to be less than 5 atom %, any effect of reducing the dielectric constant cannot be obtained. Therefore, the wiring capacitance is increased, resulting in reduction of a circuit operating speed and increase of power consumption. On the other hand, if the fluorine concentration in SiOF constituting the interlayer insulating film is set to 5 atom % or more, exfoliation of the interlayer insulating film or the wirings is more liable to occur, and the yield is reduced. That is, for the conventional semiconductor device, it has been difficult to set the optimum fluorine concentration.
SUMMARY OF THE INVENTION
The present invention has been implemented in view of the foregoing problem of the conventional semiconductor device, and according to a first aspect of the present invention, a semiconductor device having a plurality of wirings juxtaposed with one another and using SiOF insulating film, is characterized in that with respect to the insulating film, the fluorine concentration of SiOF insulating film in a wire gap portion is set to be higher than the fluorine concentration of SiOF insulating film on the wires.
Further, according to a second aspect of the present invention, a semiconductor device having a multilayer metallization wiring structure, i.e. having a plurality of wiring layers, using SiOF interlayer insulating film, is characterized in that, with respect to the interlayer insulating film, the fluorine concentration of SiOF interlayer insulating film in a wire gap portion is set to be higher than the fluorine concentration of SiOF interlayer insulating film on the wirings.
According to a third aspect of the present invention, a semiconductor device manufacturing method is characterized by comprising a step of forming a plurality of wirings on the same plane, a step of forming a first insulating film of SiOF on the plane having the plural wirings formed thereon and removing the first insulating film on the upper surfaces of the plural wirings, a step of introducing fluorine into at least the first insulating layer, and a step of forming a second insulating layer of SiOF thereon.
According to a fourth aspect of the present invention, a semiconductor device manufacturing method is characterized by comprising a step of forming a plurality of wirings on the same plane, a step of forming a first insulating film of SiOF on the plane having the plural wirings formed thereon and introducing fluorine into at least the first insulating film, a step of removing the first insulating film on the upper surfaces of the plural wirings, and a step of forming a second insulating layer of SiOF thereon.
According to the present invention, both of the reduction of the wiring capacitance and the prevention of the exfoliation of the interlayer insulating film and the wirings can be implemented.
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Imai Kiyotaka
Oda Noriaki
Lewis Monica
NEC Electronics Corporation
Scully Scott Murphy & Presser
Wilczewski Mary
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