Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2001-10-09
2004-11-09
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S262000
Reexamination Certificate
active
06816012
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high frequency power amplifiers and more particularly to techniques for combining, monolithically or otherwise, individual power amplifiers to achieve power combining and impedance transformation.
2. Description of the Related Art
The design of high frequency power amplifiers with reasonable power levels, efficiency and gain remains one of the major challenges in the pursuit of a single-chip integrated transceiver. Although several advances have been made in this direction, the design of a truly integrated power amplifier on a lossy substrate, such as silicon or silicon germanium has been an elusive goal.
Multiple external components such as bonding wires and external baluns have been used as tuned elements to produce output power levels in excess of 1W using CMOS transistors. See e.g., K. C. Tsai and P. R. Gray, “A 1.9 GHz, 1-W CMOS Class-E Power Amplifier for Wireless Communications,”
IEEE Journal of Solid
-
State Circuits
, vol. 34, no. 7, pp. 962-969, July 1999
[1]
; and C. Yoo and Q. Huang, “A Common-Gate Switched, 0.9W Class-E Power Amplifier with 41% PAE in 0.25 &mgr;m CMOS,”
Symposium on VLSI Circuits Digest
, pp. 56-57, Honolulu, June 2000
[2
]. Similar performance levels have been achieved with Si-Bipolar transistors. See, e.g. W. Simbürger, et al, “A Monolithic Transformer Coupled 5-W Silicon Power Amplifier with 59% PAE at 0.9 GHz,”
IEEE Journal of Solid
-
State Circuits
, vol. 34, no. 12, pp. 1881-1892, Dec. 1999
[3]
; and W. Simbürger, et al., “A Monolithic 2.5V, 1W Silicon Bipolar Power Amplifier with 55% PAE at 1.9 GHz,”
IEEE MTT
-
S Digest
, vol. 2, pp. 853-856, Boston, June, 2000
[4
].
Moreover, alternative technologies for active devices with higher breakdown voltages and higher substrate resistivity have been used to increase the output power and efficiency of integrated amplifiers. For example, LDMOS transistors with a breakdown voltage of 20V have been used on a semi-insulating substrate, but still this design delivers only 200 mW. See, Y. Tan, et al., “A 900-MHz Fully Integrated SOI Power Amplifier for Single-Chip Wireless Transceiver Applications,”
IEEE Solid
-
State Circ
., vol. 35, no. 10, pp. 1481-1485, October 2000
[5
]. Further, GaAs MESFET's on insulating substrates have been used to integrate power amplifiers. J. Portilla, H. Garcia, and E. Artal, “High Power-Added Efficiency MMIC Amplifier for 2.4 GHz Wireless Communications,”
IEEE Journal of Solid State Circuits
, vol. 34, no. 1, pp. 120-123, January 1999
[6
]. Unfortunately, these technologies are significantly more costly and more difficult to manufacture than conventional silicon-based transistor technologies, such as CMOS.
A summary of these prior achievements in the design of high-frequency, low voltage power amplifiers is provided in Table 1:
TABLE 1
External
Freq.
P
out
Supply
PAB
Wirebond
Compo-
Active
Ref.
(GHz)
(W)
Voltage
%
Inductor?
nents?
Device
No.
1.9
1.0
2
41
YES
YES
CMOS
[1]
0.9
1.0
1.9
41
YES
YES
CMOS
[2]
0.9
5.0
4.5
59
NO
YES
Si Bipolar
[3]
1.9
1.4
2.5
55
NO
YES
Si Bipolar
[4]
0.9
0.2
5
49
NO
NO
SOI
[5]
LDMOS
2.4
0.25
7
79
NO
NO
MESFET
[6]
Two significant problems in the design of a fully-integrated high speed solid state power amplifier using conventional silicon technologies such as CMOS are (1) the low resistivity of the lossy substrate which increases the loss of on-chip inductors and transformers; and (2) the low breakdown voltages of the transistors. These problems are exacerbated as the minimum feature sizes of the transistors (such as CMOS) are scaled down for faster operation.
More particularly, the high conductivity of lossy substrates causes long metal lines, including conventional spiral inductors fabricated on the same substrate, to be very lossy in terms of power. If the metal lines are made wide to reduce resistance, the capacitive coupling effect between the metal and substrate will drain part of the current to the substrate, thereby increasing power dissipation. On the other hand, if the metal lines are made narrow enough to effectively overcome this problem, the metal resistance will significantly increase, again absorbing (dissipating) a significant portion of the power.
The low breakdown voltage of conventional transistors such as CMOS, for example, limits the maximum allowable drain voltage swing of the transistor. This makes it necessary to perform some form of impedance transformation to achieve a larger output power. For example, a ±2V drain voltage swing delivers only 40 mW to a 50 &OHgr; load if no such impedance transformation is performed. While impedance transformation can be achieved using a 1: n transformer, unfortunately, an on-chip spiral 1: n transformer on a standard CMOS substrate is very lossy and will degrade the performance of the amplifier greatly. Alternatively, an on-chip resonant match could be used, but this technique also results in significant power loss.
In sum, as all high frequency power amplifiers ostensibly require some inductors—essentially long metal lines—for matching purposes, connections for the supplies, and some form of power combining, conventional power amplifier circuits tend to be very power inefficient and not commercially viable above certain power and frequency levels.
Thus, it would be highly desirable to have a low cost, fully integratable topology for a power amplifier that can be fabricated with low cost, silicon-based processes and that can provide significant output power levels in the microwave and millimeter-wave frequency ranges. It would also be desirable if such a topology could be implemented with discrete power amplifiers as well as monolithic integration techniques. Ideally, this architecture would also be useful in the design of both lossy substrate IC's as well as non-lossy substrate IC's.
SUMMARY OF THE INVENTION
The present invention, which addresses these needs, resides in a distributed, circular-geometry, power amplifier as a means for power combining and impedance transformation to achieve a very high output power in a small package and to overcome the low breakdown voltage of conventional active devices such as short-channel MOS transistors.
In particular, the present invention resides in a distributed, circular geometry, power amplifier for amplifying an RF input signal that comprises a plurality of smaller push-pull amplifiers. Each amplifier includes two gain blocks that each has an input port with positive and negative terminals and an output port with positive and negative terminals. The two gain blocks of each push-pull amplifier are interconnected at the positive terminals of their respective output ports by an inductive path and share a common supply voltage to the positive terminals of their respective output ports. The negative terminal of the output port of each gain block of each push-pull amplifier is connected to negative terminal of the output port of a gain block of an adjacent push-pull amplifier such that the amplifiers are configured in an interconnected circular geometry, with the connected negative terminals of adjacent gain blocks being connected together to form a virtual ac ground.
In operation, the input port of each gain block is adapted to receive an ac input signal of at least substantially equal magnitude and opposite phase relative to the input port of an adjacent gain block. The push-pull amplifiers are interconnected such that, for the fundamental frequency of operation, virtual ac-grounds are presented at the negative terminals of the output ports of the gain blocks.
In a more detailed aspect of the present invention, the distributed circular geometry power amplifier comprises at least two push-pulls amplifiers designed to amplify an RF input signal. A first push-pull amplifier includes a first gain block and a second gain block, each block having an input port with positive and negative terminals and an outp
Aoki Ichiro
Hajimiri Seyed-Ali
Kee Scott David
Rutledge David B.
California Institute of Technology
Nguyen Khanh Van
Rourk Christopher J.
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