Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-03-28
2004-06-29
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06756806
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to MOSFETS (metal oxide semiconductor field effect transistors). More particularly, the present invention relates to the field of determining location of the breakdown in a gate oxide of a MOSFET.
2. Related Art
Tremendous advances have been made in the development of metal oxide semiconductor field effect transistor (MOSFET) device. This progress has made it possible to incorporate MOSFET devices into a wider range of industrial and consumer applications. The n-type MOSFET (or NMOSFET) is formed on a p-type substrate. The p-type MOSFET (or PMOSFET) is formed on an n-type substrate. One particular development has been the dramatic reduction (or scaling) of the dimensions of a MOSFET device during the past decades, such scaling continues today. In particular, as the scaling of MOSFET devices used in VLSI (Very Large Scale Integration) chips continues, the thickness of the gate oxide of the MOSFET approaches a range of several nanometers or several sub-nanometers. For example, some state-of-the-art high-volume fabrication MOSFET devices are employing gate oxides having a thickness in the range of approximately 1.5-3 nm (nanometers). The gate oxide thickness is one of the most critical parameters of the MOSFET device.
As the thickness of the gate oxide becomes ultra thin, the dielectric breakdown (or breakdown) in the gate oxide of the MOSFET device and the reliability of the gate oxide are urgent issues needing review and analysis. The breakdown of the gate oxide becomes a major concern since the reliability of the MOSFET device (as well as circuits and products incorporating the MOSFET device) is dependent on the performance of the gate oxide. Generally, the gate oxide layer functions as an electrical insulating layer (or dielectric layer) between a gate node of the MOSFET and a substrate layer of the MOSFET. In the case of a breakdown, the insulating property of the gate oxide fails at one or more locations in the gate oxide between the gate node and the substrate layer. Under certain conditions, the MOSFET device will still function normally (with reduced performance) despite the breakdown in the gate oxide. On other occasions, the breakdown in the gate oxide causes a fatal failure in the MOSFET device, preventing it from operating properly.
Therefore, a detailed analysis of the breakdown of the gate oxide that includes determining the breakdown locations in these scaled MOSFET devices can help evaluate the performance, predict the lifetime, and improve the design of VLSI chips (as well as circuits and products incorporating the MOSFET devices). Though, lots of efforts have been made to analyze the breakdown of the oxide in large MOS (metal oxide semiconductor) capacitors, it is still difficult to locate the breakdown in the gate oxide within the scaled MOSFET devices.
What is needed is a method of determining the location of the breakdown in the gate oxide of a MOSFET. Moreover, what is needed is a method for determining the location of the breakdown that is convenient to use and can be easily employed.
SUMMARY OF THE INVENTION
A method of determining the location of the breakdown in the gate oxide of a MOSFET is disclosed. Additionally, the present invention determines the location of the breakdown in a manner that is convenient to use and can be easily employed.
According to one embodiment of the method of determining the location of the breakdown in the gate oxide of a MOSFET, a MOSFET having the gate oxide is prepared for data measurements. The method is applicable to both NMOSFETs and PMOSFETs. The method will determine whether there is a breakdown in the gate oxide. If there is a breakdown, the method will enable determination of the location of the breakdown in the gate oxide. Next, the MOSFET is configured according to a first measurement set-up. In the case of an NMOSFET, the source node of the NMOSFET is coupled to a ground, while the drain node of the NMOSFET is coupled to a first voltage. Then, a range of voltages is applied at the gate node of the MOSFET. For each applied voltage, a first set of currents is measured, whereas the first set of currents include a gate current, a source current, and a drain current. Continuing, the location of the breakdown of the gate oxide of the MOSFET is determined using the measured first set of currents. The measured first set of currents indicates whether there is a breakdown in the gate oxide. Moreover, the measured first set of currents indicates whether the breakdown is located in a channel portion of the gate oxide, in a source node overlap portion of the gate oxide, or in a drain node overlap portion of the gate oxide.
Moreover, the result of the first measurement set-up can be confirmed using a second measurement set-up. In the second measurement set-up, the source node of the MOSFET is designated as the new drain node, while the drain node of the MOSFET is designated as the new source node. In the case of the NMOSFET, the new source node is couple to the ground, while the new drain node is coupled to the first voltage. Then, a second range of voltages is applied at the gate node of the MOSFET. For each applied voltage, a second set of currents is measured, whereas the second set of currents include a gate current, a source current measured at the new source node, and a drain current measured at the new drain node. Continuing, the location of the breakdown of the gate oxide of the MOSFET is determined using the measured first set of currents and the measured second set of currents.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the drawing figures.
REFERENCES:
patent: 5594349 (1997-01-01), Kimura
patent: 6049213 (2000-04-01), Abadeer
patent: 6326792 (2001-12-01), Okada
Wang Zhigang
Yang Nian
Yang Tien-Chun
Advanced Micro Devices , Inc.
Nguyen Vinh P.
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