Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-12-04
2004-08-17
Deo, Duy-Vu (Department: 1765)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S437000, C438S691000, C438S692000
Reexamination Certificate
active
06777307
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Forming substantially planar surfaces during the processing of a semiconductor topography may involve numerous fabrication steps. For example, a layer may be deposited across a previously patterned layer of a semiconductor topography. Elevational disparities of such a deposited layer may be reduced by planarizing the layer. In some embodiments, an opening or a trench may be formed within a semiconductor topography and subsequently filled with a layer of trench fill material. In this manner, the layer of trench fill material may be formed within the opening and on an upper surface of the semiconductor surface. The layer of trench fill material may then be planarized such that an upper surface of the structure within the trench may be substantially coplanar with an upper surface of the semiconductor topography.
Substantially planar surfaces within a semiconductor topography may play an important role in fabricating overlying layers and structures. For example, step coverage problems may arise when a material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device.
A technique that is often used to planarize or remove the elevational fluctuations in the surface of a semiconductor topography is chemical mechanical polishing “CMP.” A conventional CMP process may involve placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a table or platen. During the CMP process, the polishing pad and/or the semiconductor wafer may be set into motion as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a “slurry,” may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Therefore, the CMP process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For instance, the slurry may react in recessed regions, causing those regions to be excessively etched. Furthermore, the polishing rate of the CMP may be dependent upon the polish characteristics of the topography. In addition, the polishing pad, being somewhat conformal to the surface topography, may deform in response to polishing laterally adjacent layers comprising different polish properties. Therefore, while the removal rate of raised regions of the dielectric may be greater than that of the recessed regions in a typical CMP process, a significant amount of the recessed regions may, unfortunately, undergo removal. This phenomena is known as the “dishing” effect and may reduce the degree of planarization that can be achieved by the CMP process. Consequently, the “dishing” effect may cause upper surfaces of structures and layers to curve below polished upper surfaces of adjacent structures or layers. For example, the dishing effect resulting from the fabrication of shallow trench isolation regions may be so severe that portions of the isolation regions may extend below the upper surface of the substrate. Consequently, the active regions of the device may not be adequately isolated.
To insure that the upper surfaces of structures and layers are above or coplanar with upper surfaces of adjacent structures and layers, a polish stop layer may be used to terminate the polishing process at an elevation higher than the intended height of the polished structure or layer. The composition of the polish stop layer is such that it polishes much more slowly than the layer above it. In this manner, polishing may be substantially terminated upon exposing the polish stop layer. Thus, layers or structures formed upon the semiconductor topography adjacent to the polish stop layer may also be polished to approximately the same elevation level as the polish stop layer. Silicon nitride is commonly used as a polish stop layer since it is a relatively hard material, particularly compared to silicon dioxide.
As such, a technique used to form shallow trench isolation regions, for example, may include depositing a layer of silicon nitride (“nitride”) across an upper surface of a semiconductor substrate. In some cases, a “pad” oxide layer may be interposed between the substrate and nitride layer to reduce inherent stresses between nitride and silicon. Portions of the nitride layer and substrate may be etched away to define a trench within the substrate. Fill oxide (e.g., silicon dioxide) may then be deposited into the trench to a level spaced above the upper surface of the nitride layer. The resulting upper surface of the fill oxide includes a recessed region elevationally raised above the trench area. A trench isolation region may then be formed by subjecting the semiconductor topography to a CMP process. The polish rate of the nitride layer is slower than that of the fill oxide and thus, the nitride layer may act as a polish stop layer. Subsequent to the CMP process, the nitride layer may be removed by a nitride strip followed by a selective etch technique to remove the pad oxide.
The problem of the “dishing effect” described above is particularly evident during the aforementioned method of forming shallow isolation regions. In addition to the deformation of the polishing pad and the reaction of the slurry in recessed regions of the fill oxide, the “dishing effect” may be further augmented by “overpolishing” the polish stop layer. In particular, the surface of the polish stop layer may be “overpolished” or polished to a level spaced below the original upper surface of the polish stop layer to ensure that the fill oxide no longer resides above the polish stop layer. Furthermore, the “dishing effect” may be dependent on the pattern density of the topography. For example, a topography having relatively wide spaces between the isolation regions may include a large amount of nitride across the lateral portion of the topography, which typically results in a slower polish rate. Alternatively, topographies having relatively narrow spaces between isolation regions may include less nitride across the lateral surface of the semiconductor topography, typically resulting in a faster polish rate. Consequently, a thicker layer of nitride may be needed to compensate for the increase in the polish rate. In an embodiment that includes a varied pattern density (i.e., isolation regions spaced non-uniformly across a semiconductor substrate), portions of the topography with a large of amount of nitride may be etched at a diffe
Hedayati Steven S.
Ramkumar Krishnaswamy
Cypress Semiconductor Corp.
Daffer Kevin L.
Deo Duy-Vu
Lettiang Mollie E.
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