Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2003-07-24
2004-11-23
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000, C257S691000, C257S776000, C257S782000, C257S786000
Reexamination Certificate
active
06822322
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a substrate for mounting of a semiconductor chip, and to a method for manufacturing a semiconductor device.
2. Description of the Related Art
A substrate for mounting of a semiconductor chip (mounting substrate) generally has a plurality of mounting regions as shown in FIG.
6
(A). A semiconductor device is conventionally mounted as described below.
Semiconductor chips
52
are mounted on mounting regions
60
a
-
60
d
of a mounting substrate
50
, respectively. Pads
54
of each semiconductor chip are connected by bonding wires to inner electrodes
56
of a corresponding mounting region. The mounting regions
60
a
-
60
d
are then filled with resin, and the mounting substrate
50
is diced into individual semiconductor devices.
As seen in FIG.
6
(B), inner electrodes
56
a
and
56
b
are formed on the mounting substrate
50
, and each inner electrode
56
a
,
56
b
is connected to an outer electrode via through holes (not shown). These inner electrodes
56
are generally formed by electroplating. All of the inner electrodes
56
are electrically and physically connected to each other by interconnections
58
and
59
before the mounting substrate
50
is diced along dicing line
62
into individual semiconductor devices. However, after dicing, the inner electrodes
56
should be electrically isolated from one another.
The interconnect wiring pattern
58
corresponds to the dicing line, and the interconnect wiring pattern
58
is supposed to be removed by a dicing blade during dicing the mounting substrate. However, if the position of the dicing blade is shifted, a portion of the interconnect wiring pattern
58
remains as shown in FIG.
6
(C). In some cases, the remaining portion of the interconnect wiring pattern
58
connects one inner electrode to another inner electrode, thus short-circuiting the inner electrodes.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above-described problem.
According to one aspect of this invention, for achieving the above object, A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions defined on a surface thereof, and further having a dicing line defined between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region, a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region, an interconnect wiring pattern located between the first and second chip mounting region, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connected wiring portions, and wherein at least some of said wiring pattern extend obliquely across the dicing line.
REFERENCES:
patent: 6022757 (2000-02-01), Andoh
patent: 6700186 (2004-03-01), Yasunaga et al.
patent: 6700192 (2004-03-01), Matsuzawa et al.
patent: 2001/0045630 (2001-11-01), Ikenaga et al.
patent: 2003/0098503 (2003-05-01), Ikenaga et al.
patent: 09-55398 (1997-02-01), None
patent: 2000-12989 (2000-01-01), None
Flynn Nathan J.
Mandala Jr. Victor A.
Oki Electric Industry Co. Ltd.
Volentine Francos & Whitt PLLC
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