Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
2003-05-30
2004-11-02
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S017000, C331S025000, C327S156000, C327S157000
Reexamination Certificate
active
06812797
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits, and more particularly to phase-locked loops (PLLs).
BACKGROUND OF THE INVENTION
One important application of PLLs is in clock recovery circuits. As is well known, such clock recovery circuits are commonly implemented in integrated circuits used in a wide variety of electronic systems, including communication systems, interconnection systems and data storage systems.
It is also known that PLLs used for clock recovery applications may be configured to include two related loops, generally a frequency loop and a phase loop. The frequency loop is responsible for clock signal frequency acquisition, and is designed to bring the clock signal frequency into the lock-in range of the phase loop, while the phase loop is responsible for the phase locking of the clock signal with an incoming data signal. Such PLLs are typically referred to as dual-loop PLLs, and also find application outside of the clock recovery context.
An example of a conventional dual-loop PLL is described in M. Burzio et al., “A high speed 0.7 &mgr;m CMOS PLL circuit for clock/data recovery in interconnection systems,” ESSCIRC '96 Proceedings of the 22nd European Solid-State Circuits Conference, which is incorporated by reference herein.
It is generally desirable in a dual-loop PLL that the process of switching from frequency detection using the frequency loop to phase detection using the phase loop be as smooth as possible, in order to prevent any discontinuity in loop filter state.
One previous attempt to address this issue involves keeping both loops on all the time. However, this approach can result in the injection of noise into the phase loop, thereby increasing jitter. It may also create stability problems.
Another approach to providing smooth switching from frequency detection to phase detection involves multiplexing the outputs of the frequency and phase detectors associated with the respective frequency and phase loops. However, loading problems associated with this multiplexing approach generally require the use of high-speed output circuits for one or both of the frequency and phase detectors. As a result, the circuit area and power consumption requirements of the dual-loop PLL are unduly increased.
It is therefore apparent that a need exists for an improved dual-loop PLL which can provide smooth switching from frequency detection to phase detection without the problems associated with the above-described conventional techniques.
SUMMARY OF THE INVENTION
The present invention provides an improved phase-locked loop (PLL) which in an illustrative embodiment provides loop select signal based switching between a first loop associated with frequency detection and a second loop associated with phase detection.
In accordance with one aspect of the invention, a PLL includes at least first and second loops, and loop selection circuitry coupled to the first and second loops. The loop selection circuitry is responsive to at least one loop select signal to control transition from an operating mode of one of the first and second loops to an operating mode of the other of the first and second loops.
The first and second loops may be coupled together such that the loops share at least one loop component. For example, the loops may be coupled so as to share a series combination of a signal combiner, a loop filter and a voltage-controlled oscillator.
The loop selection circuitry is preferably configured so as to provide a time interval for which the respective operating modes of the first and second loops both remain enabled prior to disabling of the operating mode of the first loop, and a time interval for which the respective operating modes of the first and second loops both remain disabled prior to enabling of the operating mode of the first loop.
In an illustrative embodiment, the PLL comprises a dual-loop PLL with the first and second loops corresponding to respective frequency and phase loops, and the loop selection circuitry is configured such that the loop select signal as applied to a control input of a current-generating component of the frequency loop represents a delayed and inverted version of the loop select signal as applied to a control input of a current-generating component of the phase loop. The current-generating components of the frequency and phase loops may comprise charge pumps.
The loop selection circuitry in the illustrative embodiment comprises a series combination of a delay element and an inverter, with the delay element configured to provide a delay on the order of approximately 100 nanoseconds. The loop select signal is applied via the series combination of the delay element and the inverter to a control input of the charge pump of the frequency loop, and is further applied to a control input of a corresponding charge pump of the phase loop. The loop select signal in the illustrative embodiment is thus utilized to control the enabling and disabling of the charge pumps of the frequency and phase loops.
A PLL in accordance with the invention may be implemented, for example, as a portion of an integrated circuit. As a more particular example, the PLL may be implemented as a component of a clock recovery circuit which is itself implemented as a portion of an integrated circuit.
Advantageously, the present invention in the illustrative embodiment provides a particularly efficient mechanism for smooth switching from frequency detection to phase detection in a dual-loop PLL. Moreover, the illustrative embodiment avoids the difficulties associated with the conventional techniques described above.
REFERENCES:
patent: 4542351 (1985-09-01), Okada
M. Burzio et al., “A High Speed 0.7&mgr;m CMOS PLL Circuit for Clock/Data Recovery in Interconnection Systems,” ESSCIRC, '96 Proceedings of the 22nd European Solid-State Circuits Conference, 4 pages, 1996.
C.R. Hogge, “A Self Correcting Clock Recovery Circuit,” IEEE Journal of Lightwave Technology, vol. LT-3. pp. 1312-1314, Dec. 1985.
Y. Tang et al., “A Non-sequential Phase Detector for PLL-based High-Speed Data/Clock Recovery,” Proceedings of 2000 Midwest Symposium on Circuits and Systems, pp. 428-431, Aug. 2000.
Chen Xinyu
De Veirman Geert Adolf
Tan Mehmet Ali
Agere Systems Inc.
Mis David
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