Semiconductor integrated circuit device and delay-locked...

Details Semiconductor integrated circuit device and delay-locked... Semiconductor integrated circuit device and delay-locked...

2002-09-12

2004-06-15

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000

Reexamination Certificate

active

06750688

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and, more particularly, to a delay-locked loop (DLL) and a semiconductor integrated circuit device equipped with the DLL.
BACKGROUND OF THE INVENTION
A DDR (Double Data Rate)-I-SDRAM (Synchronous Dynamic Random-Access Memory) is designed to perform data transfer at a transfer rate of 200 to 300 Mbps (megabits per second) with respect to an input clock having a frequency of 100 to 166 MHz. Design specification is such that data input is synchronized to both rising and falling edges of an input clock signal. The desired specifications can be achieved with a DLL of minimal structure by passing the entered clock through a single delay line as is.
FIG. 18
is a diagram illustrating an example of a DLL(Delay Locked Loop) in compliance with DDR specifications, and
FIG. 19
is a diagram illustrating the timing operation of this DLL.
Referring to
FIG. 18
, the DLL
3
A is equipped with an input buffer
1
, the inputs to which are mutually complementary clock signals CLK and CLKB transmitted in a differential mode, for outputting a clock signal CLK
1
of single-phase (single-end) mode, and includes a delay line
31
for delaying and outputting the clock signal CLK
1
input thereto from the input buffer
1
. The delay line
31
outputs the delayed signal from one output tap selected from among a plurality of output taps (not shown) whose delay times differ from one another, thereby making it possible to change the delay time.
Provided are a multiplexer (MUX)
4
, which receives two items of data read out of a memory-cell array (not shown), for selecting the data using the signal CLKOE, which is output from the delay line
31
, as a clock for data output; an output buffer
5
, which receives the output signal of the multiplexer
4
, for delivering this signal to a data output terminal as a data output signal DQj; a dummy multiplexer (MUX)
36
having a delay time identical with that of the multiplexer
4
and having the output signal CLKOE of the delay line
31
input thereto as a selection signal for outputting a HIGH- or LOW level signal; a dummy buffer
37
having a delay time identical with that of the output buffer
5
and having the output of the dummy multiplexer
36
input thereto for outputting complementary clock signals RCLK and RCLKB; a dummy buffer
38
having a delay time identical with that of the input buffer
1
and having the clock signals RCLK, RCLKB, which have been transmitted in the differential mode, input thereto for outputting a single-end clock signal CLKFBI; a phase detector
33
, to which the output signal CLK
1
of the input buffer
1
and the output signal CLKFBI of the dummy buffer
38
are input, for detecting the phase difference between the signals CLK
1
and CLKFBI; and a counter
34
for counting up or down in accordance with phase lead/lag depending upon the result of phase detection by the phase detector
33
. Fixed values of the HIGH level (VDD potential) and LOW level (VSS potential) are supplied as data to the dummy multiplexer
36
, which selects and outputs one of these values using the entered signal CLKOE as the selection signal.
In the DLL
3
A, the output tap of the delay line
31
is changed over based upon the output signal of the counter
34
in such a manner that the output clock signal CLK
1
of input buffer
1
and output signal CLKFBI of dummy buffer
38
will agree, thereby adjusting the delay time of the DLL. As shown in the timing chart of
FIG. 19
, the output signal DQj of the DDR-SDRAM is locked (synchronized) to the clock CLK.
Referring to
FIG. 19
, the timing of the rising edge of signal CLKOE is delayed by delay time td
0
of the delay line
31
relative to the timing of the rising edge of output clock CLK
1
of input buffer
1
[see arrow (
1
) in FIG.
19
]. The rising edge of the signal CLKFBI is delayed relative to the timing of the rising edge of signal CLKOE by time td
1
+td
2
+td
3
, which is the sum of delay times td
3
, td
2
, and td
1
of dummy multiplexer
36
and buffers
37
and
38
, respectively [arrow (
3
) in FIG.
19
].
Control is exercised in such a manner that the timing of the rising edge of signal CLKFBI will coincide with the timing (delayed by the delay time td
1
of the input buffer
1
relative to the starting timing of the cycle of clock CLK) of the rising edge of clock CLK
1
prevailing one cycle after the clock CLK from which the present signal CLKFBI originates.
Consequently, the timing of the rising edge of signal CLKFBI becomes
tCK+td
1
with the timing of the rising edge of input clock CLK (clock cycle=tCK) serving as the reference.
Accordingly, the timing of the rising edge of clock CLKOE becomes
tCK+td
1
−(
td
1
+
td
2
+
td
3
)=
tCK−td
2
−
td
3
In the data output propagation path through the multiplexer
4
, the propagation delay time from the rising edge of signal CLKOE to the output, of multiplexer
4
is td
3
and the propagation delay time of the output buffer
5
is td
2
[arrow (
4
) in FIG.
19
] and therefore the output timing of the data output signal DQj is
(
tCK−td
2
−
td
3
)+
td
3
+
td
2
=
tCK
In other words, the timing of the rising edge of clock CLK (the starting point of the clock cycle) and the timing at which the data output signal DQj is delivered agree.
Similarly, the timing of the falling edge of signal CLKOE is delayed by delay time td
0
of the delay line
31
relative to the timing of the falling edge of output clock CLK
1
of input buffer
1
[see arrow (
2
) in FIG.
19
]. The timing of the falling edge of the signal CLKFBI lags behind the timing of the rising edge of this signal by the pulse width of clock CLK
1
[arrow (
5
) in FIG.
19
]. The next data output signal DQj is delivered at the falling edge of the signal CLKOE, and the timing thereof coincides with the timing of the falling edge of clock CLK (the rising edge of clock CLKB). The DLL
3
A having the construction shown in
FIG. 18
is a circuit that adjusts and matches the phases of the input clock and output data and may also be referred to as an “input/output-compensating DLL”.
The specifications of a DDR-II-SDRAM are such that an even higher speed is attained, namely a clock frequency of 200 to 300 MHz (a data transfer rate of 400 to 600 mbps). In order to improve the operating margin of a memory controller, a design (Duty Cycle Correction, abbreviated to “DCC”) that synchronizes the input clock CLK to phases of 0 and 180 degrees is currently under study.
As shown by way of example in
FIG. 20
, a DLL in compliance with the specifications of a DDR-II-SDRAM is constituted by a total of four delay lines, namely a delay line (which corresponds to delay line
31
in
FIG. 18
) for 0° propagation as well as a delay line
32
for 180° propagation and two delay lines
21
and
22
for generating a 180° phase difference. In other words, this DLL circuit has a DLL
2
B for generating tCK/2 and a DLL
3
B for input/output compensation.
Referring to
FIG. 20
, the tCK/2 generating DLL
2
B includes the delay line
21
, which receives the clock signal CLK
1
from the input buffer
1
having the clocks CLK and CLKB applied thereto, for varying the delay time of its output signal CLKHF by changing over the output tap; the delay line
22
, which receives the clock signal CLKHF from the delay line
21
, for varying the delay time of its output signal CLKFBH by changing over the output tap; a phase detector
23
, which receives the clock CLK
1
and the output signal CLKFBH of delay line
22
, for detecting the phase difference between these two signals; and a counter
24
for counting up or down in accordance with phase lead/lag depending upon the result of phase detection by the phase detector
23
. The output taps of the delay circuits
21
and
22
are selected in such a manner that the timings of the rising edges of the signals CLKFBH and CLK
1
(CLK
1
one cycle later than the cycle o

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