Parallel processing system for time division multiplex data tran

Details Parallel processing system for time division multiplex data tran Parallel processing system for time division multiplex data tran

1994-07-27

1998-01-13

Lee, Thomas C.

395297, 395304, 395458, 395476, G06F 1516, G06F 938

Patent

active

057088500

ABSTRACT:
Disclosed is a multiprocessor system made up of several processing nodes linked by a time division multiplexed (TDM) bus to form a synchronous system. According to one embodiment, each processing node includes a digital signal processing (DSP) element, a dual port memory element and a memory control element in an integrated structure. Each memory element is segmented into four quarters. The first two are for read operations by the DSP element and write operations by the bus. However, the DSP element and the bus can only access any given segment during opposite phases of a frame clock signal. Additionally, each node is assigned an exclusive identification code whereby each node can post data to a memory element of another node.
According to another embodiment, the various elements of each node are combined in various integrated structures.

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"Pipelined, Time-Sharing Access Technique for a Highly Integrated Multiport Memory", Matsumura et al, IEEE, pp. 107-108, Feb. 1990.

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