Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-23
2004-06-08
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S042000
Reexamination Certificate
active
06747901
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device.
The flash memory most commonly used today is an ETOX (Trademark of Intel Co.). A schematic cross sectional view of a floating-gate field-effect transistor of this ETOX-type flash memory cell is shown in FIG.
9
. The floating-gate field-effect transistor is provided with a source
73
and a drain
74
formed on a substrate
71
, a floating gate
76
formed over between the source
73
and the drain with a tunnel oxide
75
interposed therebetween, and a control gate
78
formed on the floating gate
76
with an interlayer insulating film
77
interposed therebetween.
Description will be now given of an operational principle of the ETOX-type flash memory. Table 1 below describes voltage conditions in writing, erasing, and reading operation.
TABLE 1
Control
gate
Drain
Source
Substrate
Writing
10 V
6 V/0 V
0 V
0 V
Erasing
−9 V
OPEN
4 V
0 V
Reading
5 V
1 V
0 V
0 V
In writing operation, as shown in Table 1, a voltage Vpp (ex., 10V) is applied to the control gate
78
, a reference voltage Vss (ex., 0V) is applied to the source
73
, and a voltage of 6V is applied to the drain
74
. Consequently, a large current flows through a channel region between the source
73
and the drain
74
, and hot electrons are generated in an area with high electric fields on the drain side, by which electrons are injected into the floating gate
76
. As a result, a threshold value is increased, which activates a program state. The threshold value in the program state is shown in FIG.
10
.
In erasing operation, a voltage Vnn (ex., −9V) is applied to the control gate
78
, and a voltage Vpe (ex., 4V) is applied to the source
73
, so that electrons are pulled toward the source side from the floating gate
76
and the threshold value is decreased, thereby activating an erased state. The threshold value in the erased state is shown in FIG.
10
.
In such erasing operation, a BTBT (Band To Band Tunneling) current flows, while at the same time, hot holes and hot electrons are generated. The hot electrons flow away in a substrate direction, whereas the hot holes are pulled toward the tunnel oxide
75
side and trapped inside the tunnel oxide
75
. Generally, this phenomenon is considered to be a cause of deteriorated reliability of flash memories.
In reading operation, a voltage of 1V is applied to the drain
74
, a voltage of 0V is applied to the source
73
, and a voltage of 5V is applied to the control gate
78
. Herein, if the threshold value is in the erased state and low, current flows into a memory cell and status of the memory cell is determined to be “1”. If the threshold value is in the program state and high, current does not flow into a memory cell, and status of the memory cell is determined to be “0”.
As described above, this kind of operation method has a problem that a BTBT current generated in the erasing operation causes deteriorated reliability of the memory cells. One solution to this problem is a channel erasing operation which does not generate the BTBT current at the time of erasing. A nonvolatile semiconductor memory device with use of the channel erasing is disclosed in Japanese Patent Laid-Open Publication HEI No. 11-39890. In the Japanese Patent Laid-Open Publication HEI No. 11-39890, writing and reading operation is performed in the same way as the above-stated method.
Hereinbelow, description will be made of the channel erasing operation with reference to FIG.
11
. As shown in
FIG. 11
, each floating-gate field-effect transistor Tr is provided with a source
113
and a drain
114
formed inside a P-type well
112
provided inside an N-type well
111
on a semiconductor substrate
110
, a floating gate
116
formed over between the source
113
and the drain
114
with a tunnel oxide
115
interposed therebetween, and a control gate
118
formed on the floating gate
116
with an interlayer insulating film
117
interposed therebetween. Reference numeral
119
denotes a channel region.
In erasing operation, a voltage Vnn (ex., −9V) is applied to the control gate
118
through a word line WL, when a voltage Vesc (ex., +6V) is applied to the source
113
and the P-type well
112
. Consequently, strong electric fields are applied to the tunnel oxide
115
of the floating-gate field-effect transistor Tr. As a result, an FN (Fowler-Nordheim) tunneling phenomenon occurs, which causes electrons in the floating gate
116
to be pulled out, resulting in decreased threshold value. Voltage application conditions in this case are outlined in Table 2 below.
TABLE 2
Control
P-type
N-type
gate
Drain
Source
well
well
Writing
10 V
6 V/0 V
0 V
0 V
3 V
Erasing
−9 V
OPEN
6 V (or
6 V
6 V
OPEN)
Reading
5 V
1 V
0 V
0 V
3 V
In erasing operation, as shown in Table 2, potential of the source
113
is equal to potential of the P-type well
112
, so that electric fields are not concentrated onto an interface between the source
113
and the P-type well
112
, and therefore the BTBT current is not generated. As a result, hot holes are not trapped in the tunnel oxide
115
, which improves reliability of the memory cells, i.e., reliability of the floating-gate field-effect transistor Tr.
Description is herein given of a voltage supply circuit for executing channel erasing. The voltage supply circuit is provided with a positive voltage pumping circuit
101
and a negative voltage pumping circuit
103
. The positive voltage pumping circuit
101
is connected to an N-type well
111
on a substrate
110
and a P-type well
112
via a well switch
104
. The negative voltage pumping circuit
103
is connected to a control gate
118
of the floating-gate field-effect transistor Tr via a row decoder RD. The control gate
118
and the row decoder RD are connected by a word line WL.
According to the above-structured voltage supply circuit, when erasing operation is started, the negative voltage pumping circuit
103
operates to output a negative voltage (ex., −9V) to the word line WL. Consequently, a voltage of −9V is applied to the control gate
118
. At this time, the positive voltage pumping circuit
101
also operates to apply a positive voltage (ex., 6V) outputted by the positive voltage pumping circuit
101
to the N-type well
111
and the P-type well
112
.
FIG. 12
shows a circuit diagram of the well switch
104
. The well switch
104
is composed of an NAND gate
121
, a voltage level shifter
122
, a P-type MOS (Metal Oxide Semiconductor) FET
123
, and an N-type MOSFET
124
. A voltage of 6V is outputted to the N-type well
111
and the P-type well
112
when the P-type MOSFET
123
is set to ON state by an Erasesp signal.
Upon completion of pulse application, there is executed a shutdown sequence for setting the P-type well
112
and the word line WL to have a reference voltage (Vss). More particularly, an Erasesp signal becomes low, voltage of the word line WL is forced to be a reference voltage Vss, and voltage of the P-type well
112
is forced to be a reference voltage Vss.
Finally, the positive voltage pumping circuit
101
and the negative voltage pumping circuit
103
are stopped.
FIG. 13
shows one example of voltage waveforms of the word line WL, the N-type well
111
, and the P-type well
112
at this point. As shown in
FIG. 13
, with timing that voltage of the word line WL (referred to as a word line WL voltage in
FIG. 13
) is forced to be a reference voltage Vss, voltage of the P-type well
112
(referred to as a P-well voltage in
FIG. 13
) increases by approx. 2V from 6V to approx. 8V. After that, voltage of the P-type well
112
is forced to be 0V. It is noted that N-well voltage in
FIG. 13
refers to voltage of the N-type well
111
.
Such voltage change in the P-type well
112
causes a following problem.
As shown in
FIG. 11
, a negative voltage pumping circuit
103
is connected to the word line WL for supplying a negative voltage. In erasing operation, it applies a voltage of −9V to the word line WL. A positive voltage pump
Ho Hoai
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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