Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2000-06-08
2004-11-02
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S018000, C716S030000, C716S030000
Reexamination Certificate
active
06813597
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to synthesis of electronic circuits. The invention is also related to the reuse of circuit designer knowledge. The invention is more particularly related to the synthesis of analog circuitry, and of mixed digital and analog circuitry. The invention is yet further related to the simulation of mixed analog and digital circuitry to determine data points and to curve fit the data points to determine a polynomial equation that closely approximates simulated circuit performance. The invention is still further related to the parameterization of circuit features with respect to circuit performance.
BACKGROUND OF THE INVENTION
The field of circuit simulations has many design languages, simulators, and design programs available to circuit design engineers. One commonly utilized design language is the Verilog® (a registered trademark of Cadence Design Systems, Inc.).
Verilog® is a hardware description language that provides a means of specifying a digital system at a wide range of abstraction levels. The language supports the early conceptual stages of design with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description.
Other analysis tools have been developed around the Verilog® language, including fault simulators, and timing analyzers, and the language has provided input specification for some logic and behavioral synthesis tools. The language has been standardized as IEEE standard #1364-1995, and is described in detail in “The Verilog® Hardware Description Language,” by Donald E. Thomas and Phillip R. Moorby, and is incorporated herein by reference.
Analog circuits are commonly simulated by SPICE (Simulation Program with Integrated Circuit Emphasis), a commercially available software program for simulating analog circuits. SPICE frees engineers from the laborious, and often complex, time consuming tasks of analog circuit analysis. SPICE was originally developed by a team at the University of California at Berkeley and consists of a set of powerful algorithms for a wide range of circuit analysis methods. Many of SPICE function have been implemented on a personal computer platform, as described in “The Illustrated Guide to PSPICE®” by Robert Lamey, which is incorporated herein by reference.
As with Verilog®, the SPICE language has been utilized in many other tools and simulations. In addition, various vendors and groups have attempted to apply similar principles to analog synthesis such as module generators (OPASYN, CADICS, and ADORE from UC Berkeley, and VASE from University of Cincinnati, for example) and topology optimizers (IDAC/ILAC or AutoLinear marketed by Silicon Compiler Systems, AMGIE by Leuven, ASTRX/OBLX by CMU, for example). However, no tools provided either commercially available tools or true synthesis of analog or mixed analog regardless of the underlying description languages or simulators.
SUMMARY OF THE INVENTION
The present inventors have realized that analog and mixed signal synthesis may be performed. Roughly described, the present invention allows a top down design of mixed-signal systems and combines a high performance, mixed mode, single kernel simulation with behavioral modeling of circuits, automated characterization, a mixed-signal cell library, and optimization algorithms.
The present invention performs computer aided design and realization of analog circuits. The realized analog circuits may be provided in any form, but are currently provided as fully dimensioned circuits or netlists that meet a users selected performance constraints and can be laid out (placed and routed) in a selected semiconductor technology.
The present invention meets at least two broad design objectives:
1. Increase productivity of the analog and mixed signal designer; and
2. Extend design capabilities.
The objectives are met by capturing the knowledge of an expert circuit designer (or cell designer/plan author) in how a circuit is constructed and partitioned, how to propagate higher level performance constraints to the lower, cell level, and in what order to synthesize the cells. The non-creative objectives met include activities like characterization, optimization, and simulation, once options and parameters for these activities have been decided.
Therefore, the benefits of using Antrim-MSS for analog design can be summarized as:
1. Capture of designer knowledge;
2. Shorten design cycle by automating time-consuming aspects of design, allowing the designer to focus on actual design issues; and
3. Make designer knowledge re-usable.
Benefits for extending design capability, include:
1. Enabling a top-down mixed signal design methodology; and
2. Execution of design plans without requiring a high level of analog expertise.
The invention is implemented by a synthesis engine that utilizes pre built plans for circuit design that include basic circuit topologies and paramaterized design criteria that has been fitted to a polynomial expression that synthesizes the circuit's operation. A plan author first builds a synthesis library of circuit designs and one or more plans for a specific circuit being designed or for general use. The plan captures the expert knowledge of the plan author for that specific type of circuit. Following users may then use the similar plan and need not know any particular details for designing that type of circuit.
In operation, a user of the present invention selects a plan from a synthesis library, and specifies a set of performance criteria, and the synthesis engine calculates a circuit fitting the input performance criteria. The synthesis engine outputs a sized netlist or other identification of the circuit design, a simulation script for later verification of circuit performance, and performance specs in the form of a datasheet.
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Cadence Design Systems Inc.
Fliesler & Meyer LLP
Phan Thai
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