Jitter tolerance improvement by phase filtration in...

Details Jitter tolerance improvement by phase filtration in... Jitter tolerance improvement by phase filtration in...

2001-06-27

2004-08-24

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S313000

Reexamination Certificate

active

06782404

ABSTRACT:

TECHNICAL FIELD
This invention pertains to adaptive and programmable improvement of jitter tolerance margins in feed-forward data recovery systems using statistical correlating digital phase-filtering techniques.
BACKGROUND
High speed digital communications networks require very accurate time synchronization throughout the network. This is accomplished by incorporating “clock-recovery” circuits in key network components such as add/drop multiplexers, digital cross-connects, regenerative repeaters, etc. Such circuits extract timing signals embedded in the transmitted data. The extracted timing signals are used to control sampling and retiming of the received data. However, noise can cause the period of a received data signal to fluctuate or “jitter”. The extracted timing signals must remain in synchronization with the data, irrespective of jitter.
For purposes of this invention, a clock recovery circuit's “jitter tolerance” is representative of the maximum amount of jitter that can be imposed on a timing signal processed by the circuit without impairing the circuit's ability to produce a jitter-free replica of the timing signal. Typical clock recovery circuits have very high jitter tolerance (exceeding 1 Unit Internal (UI)) at lower jitter frequencies, but have significantly degraded jitter tolerance when processing signals having high frequency jitter content.
Prior art clock-recovery circuits are typically based on phase-locked loop (PLL) or surface acoustic wave (SAW) filters, with PLLs being more common in view of the high cost of SAWs. Analog PLLs, typically comprising a phase detector, voltage-controlled oscillator (VCO) and a low pass filter, are undesirable in spite of their highly accurate performance, due to their relative complexity, large power consumption and large integrated circuit surface area requirements.
Digital data recovery systems, such as feed-forward over-sampled architectures have been developed to reduce the large power consumption and integrated circuit surface area requirements of analog systems. Prior art over-sampled architectures can perform very high speed phase detection with good low frequency jitter margins. However, such architectures are subject to significant degradation of jitter tolerance if subjected to high frequency jitter and low transition data.
More particularly, high speed phase tracking at very high frequencies is susceptible to unwanted tracking of uncorrelated high frequency noise components such as duty-cycle distortion, pattern dependent jitter (also known as inter-symbol interference or ISI), high frequency noise on data over-sampling clock phases (resulting in abrupt movement of the reference phases) or glitchy transition detection (due mostly to metastability problems in the front-end samplers). Most such noise components bear no correlation to the relatively lower frequency deterministic component of noise or phase change.
Prior art systems which are incapable of distinguishing between such high frequency uncorrelated noises and their lower frequency deterministic counterparts are error prone. The jitter tolerance of such systems is reduced well below the theoretical maximum of (1-phase quantization step) UI peak-to-peak, to a theoretical minimum of (phase quantization step—non-idealities) UI peak-to-peak. phase quantization step (or phase quantization noise) is the minimum phase step which cannot be further broken down and distinguished by the system. In a q-times over-sampled architecture, the phase quantization step is q
−1
UI peak-to-peak. non-idealities (which tend to further reduce jitter tolerance) include factors such as input offset at the data sampler's front end, duty cycle distortion on the data, etc.
FIGS. 1
,
2
and
3
illustrate the prior art's significant degradation of jitter tolerance at high speed.
FIG. 1
depicts a conventional feed-forward over-sampled data recovery scheme with a four-bit segment of an ideal, jitter-free data signal
10
representing the bit pattern “1010”. Each four-bit segment is 5-times over-sampled (i.e. q=5), reducing the data rate required in the subsequent pipelined processing circuitry by a factor of four, with the five sampling clock phases
12
(i.e. &phgr;
2
, &phgr;
3
, &phgr;
4
, &phgr;
5
) ideally being equally spaced apart by 0.2 UI over the four bit segment.
FIG. 3
is a phase-circle diagram depicting a 1 UI bit period divided into five phase periods &phgr;
1
, &phgr;
2
, &phgr;
3
, &phgr;
4
, &phgr;
5
arranged in a circle, with bit boundary
31
shown, by way of example only, between &phgr;
1
and &phgr;
5
. Each phase period corresponds to 0.2 UI, as noted above.
Returning to
FIG. 1
, “bit 1” is sampled five times at sampling clock phases &phgr;
1
1
, &phgr;
2
1
, &phgr;
3
1
, &phgr;
4
1
, and &phgr;
5
1
; “bit 2” is sampled five times at sampling clock phases &phgr;
1
2
, &phgr;
2
2
, &phgr;
3
2
, &phgr;
4
2
, and &phgr;
5
2
; “bit 3” is sampled five times at sampling clock phases &phgr;
1
3
, &phgr;
2
3
, &phgr;
3
3
, &phgr;
4
3
, and &phgr;
5
3
; and, “bit 4” is sampled five times at sampling clock phases &phgr;
1
4
, &phgr;
2
4
, &phgr;
3
4
, &phgr;
4
4
, and &phgr;
5
4
. The twenty resultant over-sampled bits are exclusive-or'd, in adjacent pairs, by one of twenty exclusive-or gates
14
to produce, at outputs
16
, twenty binary signals representative of the 0-to-1 and 1-to-0 bit transitions in signal
10
. For example, the leftmost exclusive-or gate shown in
FIG. 1
produces a “1” output signal representative of the 0-to-1 bit transition in the trailing edge portion of bit
1
during sampling clock phase &phgr;
1
1
, etc.
The corresponding phase portions of bit transition output signals
16
are summed to produce a weighted sum for each of the five phases implicit in the aforementioned 5-times over-sampling of signal
10
. Specifically, combiner
18
produces an output signal &phgr;
1
sum representative of the sum of the 1
st
phase over-sampled portions &phgr;
1
1
, &phgr;
1
2
, &phgr;
1
3
, &phgr;
1
4
of bits
1
,
2
,
3
and
4
respectively; combiner
20
produces an output signal &phgr;
2
sum representative of the 2
nd
phase over-sampled portions &phgr;
2
1
, &phgr;
2
2
, &phgr;
2
3
, &phgr;
2
4
; combiner
22
produces an output signal &phgr;
3
sum representative of the 3
rd
phase over-sampled portions &phgr;
3
1
, &phgr;
3
2
, &phgr;
3
3
, &phgr;
3
4
; combiner
24
produces an output signal &phgr;
4
sum representative of the 4
th
phase over-sampled portions &phgr;
4
1
, &phgr;
4
2
, &phgr;
4
3
, &phgr;
4
4
; and, combiner
26
produces an output signal &phgr;
5
sum representative of the 5
th
phase over-sampled portions &phgr;
5
1
, &phgr;
5
2
, &phgr;
5
3
, &phgr;
5
4
.
The five weighted summation signals &phgr;
1
sum, &phgr;
2
sum, &phgr;
3
sum, &phgr;
4
sum and &phgr;
5
sum are input to 5-way comparator
28
which determines the summation signal having the greatest weight and outputs a signal representative thereof to data selector
30
. As
FIG. 1
clearly shows, in the absence of jitter on signal
10
, combiner
18
receives four “1” input signals, whereas each of combiners
20
,
22
,
24
and
26
receive four “0” input signals. Accordingly, the summation signal &phgr;
1
sum produced by combiner
18
clearly outweighs the summation signals produced by any one of combiners
20
,
22
,
24
and
26
. Consequently, 5-way comparator
28
correctly outputs to data selector
30
a signal representative of the fact that the 0-to-1 and 1-to-0 bit transitions in signal
10
occur during the 1
st
phase (i.e. &phgr;
1
) over-sampled portions &phgr;
1
1
, &phgr;
1
2
, &phgr;
1
3
, &phgr;
1
4
, of bits
1
,
2
,
3
and
4
respectively, thereby facilitating accurate recovery of signal
10
by subsequent processing circuitry (not shown). If 5-way comparator
28
determines that two phases have equally high weighting, it invokes an arbitration scheme to select one of those two phases.
Now consider
FIG. 2
, which is identical to
FIG. 1
except that a jittered version
10
A of data signal
10
is to be recov

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