DC offset cancel circuit

Details DC offset cancel circuit DC offset cancel circuit

2003-01-23

2004-02-10

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S560000

Reexamination Certificate

active

06690225

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from each of the prior Japanese Patent Application No. 2002-28469 filed on Feb. 5, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to cancellation of DC offset component that is likely to be included in an output signal, more particularly to a receiver used for mobile communication such as cellular phones.
2. Description of Related Art
Mobile communication appliances such as cellular phones rapidly prevailing in recent years need to meet demands on miniaturization, weight saving, and multi-function design. To meet such demands, in place of superheterodyne system conventionally used for a radio processing section, there has been widely employed direct conversion system that does not require an intermediate frequency signal (IF signal) and directly converts a radio frequency signal (RF) into a baseband signal. Since this system does not require a section for processing an IF signal, circuit scale of it can be compressed more than that of the superheterodyne system, which contributes to miniaturization, weight saving, and multi-function design of mobile communication appliance kind.
However, since the direct conversion system directly converts an RF signal into a baseband signal, this system cannot remove unnecessary DC offset components whereas DC offset components in an IF signal were removed by a band-pass filter or the like in the superheterodyne system. Accordingly, the direct conversion system requires a particular circuit for canceling DC offset.
FIG.
5
through
FIG. 8
show examples of DC offset cancel circuits conventionally used. Out of those, examples of circuit structure shown in FIG.
5
through
FIG. 7
are suitable for communication system such as called FDMA (frequency division multiple access), CDMA (code-division multiple access) or the like. FDMA and CDMA are communication system for receiving RF signals that succeed in terms of time. On the other hand, circuit structure shown in
FIG. 8
is suitable for communication system such as called TDMA (time division multiple access) or the like. TDMA is communication system for receiving RF signals that do not succeed in terms of time. In the following descriptions, against TDMA system, communication system for receiving RF signals that succeed in terms of time will be mentioned as non-TDMA system.
It should be noted that FDMA (frequency division multiple access) is communication system that different frequencies are allocated to respective channels and CDMA (code-division multiple access) is communication system that different codes are allocated to respective channels. In both FDMA and CDMA, receiving signals succeed in terms of time. On the other hand, TDMA (time division multiple access) is communication system that channels are allocated to time slots each of which has its predetermined time length and RF signals circulate in each channel. Accordingly, receive operation is conducted in predetermined time slots only.
FIG. 5
shows circuit structure
110
directed to first prior art. In the circuit structure
110
, there are provided highpass filters (HPF)
101
, and
102
in signal paths that lead to differential output signals OUT, XOUT from differential input signals IN, XIN, respectively, through an amplifier (AMP)
10
, whereby DC offset is cancelled. In
FIG. 5
, the highpass filters (HPF)
101
, and
102
are provided at input side and output side of the amplifier (AMP)
10
, respectively, whereby DC offset components are cut out in double. Other than this manner of DC offset cancellation, the first prior art can be structured with either one of the highpass filters (HPF). There are structured the highpass filters (HPF)
101
, and
102
including capacitor elements in the signal paths, and, on demand, further including resistance elements between output side of the capacitor elements and reference voltage. In the circuit structure
110
, DC offset is filtered in a form of analog signal and finally cancelled. Circuit structure as such is suitable for non-TDMA system where signals that succeed in terms of time are dealt.
FIG. 6
shows circuit structure
120
directed to second prior art. In the circuit structure
120
, differential output signals OUT, XOUT are integrated by an integration circuit
103
and fedback to differential input signals IN, XIN, whereby DC offset is cancelled. The integration circuit
103
is constituted by a comparator
15
and a time constant circuit that is constituted by connecting two couples of a resistance element and a capacitor element (R
101
and C
101
, R
102
and C
102
) between differential input side and differential output side of the comparator
15
. Differential output signals OUT, XOUT inputted through the resistance elements R
101
and R
102
include AC signal components as AC component and DC offset component as DC component. However, the integration circuit
103
integrates the differential output signals OUT, XOUT depending on time constant determined by the two couples of resistance element and capacitor element (R
101
and C
101
, R
102
and C
102
) and only predetermined DC offset components of those signals are feedback to an amplifier (AMP)
10
. Although
FIG. 6
shows structure that a feedback signal is directly fedback to differential input signals IN, XIN, it is possible to feedback a feedback signal to a point other than the input signals IN, XIN if it is a point capable of adjusting DC offset components of the amplifier (AMP)
10
. For example, a feedback signal can be feedback to a bias current source to an input-stage differential pair of the amplifier (AMP)
10
. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
It should be noted that the comparator
15
is a circuit that has a predetermined gain and outputs a signal depending on differential signals of differential output signals OUT, XOUT.
FIG. 7
shows circuit structure
130
directed to third prior art. In the circuit structure
130
, differential output signals OUT, XOUT are compared at a comparator
15
and differential output signals as comparison result are fedback to an amplifier (AMP)
10
through a lowpass filter constituted by two couples of a resistance element and a capacitor element (R
103
and C
103
, R
104
and C
104
), whereby DC offset is cancelled. The differential output signals OUT, XOUT and the comparison result include AC signal components as AC component and DC offset components as DC components. However, only predetermined DC offset components are extracted by the lowpass filter
104
and fedback to the amplifier (AMP)
10
. Different from the case of
FIG. 6
,
FIG. 7
is structured such that a feedback signal is feedback to an internal circuit such as bias current source to an input-stage differential pair of the amplifier (AMP)
10
. The circuit structure
130
filters analog signals through the lowpass filter
104
and calculates a correction value of DC offset components. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
FIG. 8
shows circuit structure
140
directed to fourth prior art. In the circuit structure
140
, differential output signals OUT, XOUT are compared at a comparator
15
and then, converted into digital signals by an AD converter
107
. To these digital signals, digital processing is applied by a digital signal processing circuit (DSP)
108
so as to output correction signals against DC offset components. Since the correction signal is a digital signal, the signal is converted into an analog signal by a DA converter
109
and fedback to an amplifier (AMP)
10
. In case a predetermined time slot in a predetermined communication time cycle is set as offset-quantity detecting time like TDMA system, a correction value obtained by signal processing and calculation is stored in the digital signal processing circuit (DSP)

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