Semiconductor storage unit

Details Semiconductor storage unit Semiconductor storage unit

2002-09-25

2004-08-10

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Powering

C365S063000, C365S230030

Reexamination Certificate

active

06775198

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage unit, and more specifically, to a control of power supply for driving a dynamic random access memory.
2. Description of the Background Art
FIG. 1
is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as “DRAM”) chip
70
. The conventional DRAM chip
70
has memory banks A, B, C, and D arranged in areas obtained by dividing a rectangular semiconductor chip into 4 portions. Each of memory banks A through D has, for example, 16M-bit storage capacity, and further includes a line address decoder which selects lines of the bank, column address decoder which selects columns, and a sense amplifier which detects and amplifies data of memory cell selected (none of them is illustrated).
Furthermore, DRAM chip
70
has two kinds of power supply circuit which drives each of memory banks A through D. That is, peripheral power supply circuits VDC
71
,
72
,
73
, and bank power supply circuits for VPP
74
,
75
. Peripheral power supply circuits VDC
71
,
72
,
73
supply power (that is, current and line voltage) to peripheral circuits and one or more sense amplifiers. On the other hand, bank power supply circuits for VPP
74
and
75
apply the power (that is, current and step-up voltage VPP) to word lines selected. All of the power supply circuits are installed at central regions defined between a row of memory banks A and C of DRAM chip
70
and a row of memory banks B and D. One of the reasons why a power supply circuit is arranged at the central region is that lengths of power supply lines which apply line voltage to memory banks A through D are brought to be nearly equal.
When memory cell selecting operations are carried out simultaneously in memory banks A through D, peripheral power supply circuit VDC must supply electric power to sense amplifiers included in memory banks A through D. That is, a drive transistor of peripheral power supply circuit VDC which supplies current and voltage to a sense amplifier needs to have a large current driving power. Consequently, size (channel width) of drive transistor must be made sufficiently large. However, since the current flows through a drive transistor which has a large channel width when a sense amplifier is in operation, it is unable to reduce direct current, and as a result, current consumption of DRAM chip
70
increases.
In addition, peripheral power supply circuits VDC
71
,
72
,
73
are not arranged at positions completely at equal distances from memory banks A through D. Consequently, impedance of power supply line differs due to the difference of the length of power line and the drop rate of line voltage supplied to the power supply line also differs. When the power supply capability of peripheral power supply circuits VDC
71
,
72
,
73
is decided with voltage drop in the power supply line with small impedance, still greater voltage drop occurs in the sense power supply line with large impedance, and accurate sense operation is unable to be carried out. On the other hand, when the current driving force of peripheral power supply circuits VDC
71
,
72
,
73
is decided with voltage drop in the power supply line with large impedance, unnecessarily large current is supplied to the sense power supply line with small impedance, and current is consumed. That is, because of unbalance of impedance in the power supply line, stable operation of DRAM chip
70
is unable to be secured.
SUMMARY OF THE INVENTION
It is an object of the present invention to supply electric power that enables each memory bank to stably operate and at the same time to reduce consumption power.
A semiconductor storage unit according to the present invention has multiple arrays that form memory banks on a substrate, each of the memory banks consisting of two of the multiple arrays; first power supplies, each of which supplies driving power to a peripheral circuit which drives each of the multiple arrays; and second power supplies, each of which supplies access power to word lines which access the multiple arrays. Multiple arrays are arranged in the form of a matrix and surround the central region of the substrate. The first power supplies are mounted to a central region side and to an opposite side of the central region side for predetermined arrays. The second power supplies are arranged at four corners of the central region. The first power supplies serve as a main power supply to provide main power and as an auxiliary power supply to provide auxiliary power, smaller than the main power, and provide distantly arranged two of the multiple arrays forming a memory bank with power. According to this configuration, even for memory bank arrays which are arranged distantly, sufficient electric power can be applied with voltage drop avoided.


REFERENCES:
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 6021080 (2000-02-01), Miyano
patent: 6064621 (2000-05-01), Tanizaki et al.
patent: 6195306 (2001-02-01), Horiguchi et al.
patent: 6222781 (2001-04-01), Matsumoto et al.
patent: 11-203862 (1999-07-01), None

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