Optics: measuring and testing – Inspection of flaws or impurities – Surface condition
Reexamination Certificate
2002-05-07
2004-11-16
Rosenberger, Richard A. (Department: 2877)
Optics: measuring and testing
Inspection of flaws or impurities
Surface condition
C356S128000, C438S630000
Reexamination Certificate
active
06819417
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of monitoring the quality of silicided surfaces.
(2) Description of the Prior Art
The creation of semiconductor devices applies various techniques such as creating surface regions of different conductivity by impurity ion implantation, the growth of overlying layers of epitaxy and the diffusion of implanted impurity ions. All of these techniques have specific objectives such as creating regions of conductivity or the establishment of low-resistivity contact regions to semiconductor devices. This latter approach is notably used in establishing contact surfaces to points of contact of CMOS devices. A CMOS device in it simplest form comprises a gate electrode with impurity ion implantations having been provided into the surface of the substrate over which the gate electrode is created. Contact plugs are provided to the source/drain regions of the gate electrode and to the surface of the gate electrode. Where these contact plugs interface with the contacted regions, special surface interfaces are provided to assure a low-resistivity interface, optimizing device performance.
FIG. 1
shows a cross section of a conventional CMOS device, the creation of this device will be briefly highlighted using the device elements that are highlighted in FIG.
1
. The process of creating a CMOS device starts by providing a semiconductor substrate
10
, FIG.
1
. Insulation regions
12
, that bound the active region in the surface of substrate
10
, isolate the active region and may comprise regions of Field Oxide (FOX) isolation or Shallow Trench Isolation (STI). A thin layer
14
of gate oxide is grown over the surface of the substrate
10
in the active device region. To create the gate structure, a layer
16
of polysilicon is grown over the thin layer
14
of gate oxide. The polysilicon layer
16
is masked and the exposed polysilicon
16
and the thin layer
14
of oxide are etched to create the polysilicon gate
16
that is separated from the substrate
10
by the remaining thin layer
14
of oxide. The doping of the source/drain regions starts with creating the lightly N
+
doped diffusion (LDD) regions
11
. The sidewall spacers
24
for the gate structure are formed after which the source (
13
) and drain (
15
) regions doping is completed by doping the source/drain regions
13
/
15
to the desired level of conductivity using an impurity implantation.
Low resistivity contact point
18
to the source (
13
) and contact point
20
to the drain (
15
) regions and contact point
22
to the electrode gate (
16
) are then formed by first depositing a layer of for instance titanium over the surface of the source/drain regions and the top surface of the gate electrode. This titanium is annealed, causing the deposited titanium to react with the underlying silicon of the source/gain regions and the doped surface of the gate electrode. This anneal forms layers of titanium silicide
18
/
20
on the surfaces of the source/drain regions
13
/
15
and layer
22
on the top surface of the gate electrode
16
.
Metal contact
28
with the source (
13
) region, metal contact
30
with the drain (
15
) region and metal contact
32
with the gate electrode (
16
) are formed as a final step. A layer
26
of dielectric, such as silicon oxide, is blanket deposited over the surface of the created structure. This layer of dielectric is patterned and etched to create contact openings
27
/
29
over the source/drain regions
13
/
15
and opening
31
over the top surface of the gate electrode
16
. A metallization layer is deposited over the patterned layer
26
of dielectric, establishing the electrical contacts
28
/
30
with the source/drain regions
13
/
15
and
32
with the top surface of the gate electrode
16
.
The invention addresses concerns of damage that occurs to the surface of the source/drain regions during processing steps of plasma wet etching, which are required for the etching of gate spacers
24
and which are required for the creation of openings
27
/
29
through the layer
26
of dielectric. The quality of the silicided surface
18
/
20
degrades as a consequence of these plasma etching procedures, resulting in reduced molecular smoothness of these surface (that is: poor surface morphology) and in high sheet resistance of the surfaces of layers
18
/
20
.
U.S. Pat. No. 6,141,103 (Pinaton et al.) shows a method using refractive index to monitor an I/I process.
U.S. Pat. No. 61,052,185 (Banet et al.) reveals a method using a laser to determine concentrations in wafers.
U.S. Pat. No. 5,578,161 (Auda) discloses a method to monitor trenches using spectrometers.
U.S. Pat. No. 5,321,264 (Kuwabara et al.) and U.S. Pat. No. 5,042,952 (Opsal et al.) show methods to measure wafer surface properties using Index of refraction and other methods.
SUMMARY OF THE INVENTION
A principle objective of the invention is to monitor and thus remove the potential for damage to the source/drain surface regions of a silicon substrate during plasma etching.
Another objective of the invention is to monitor and thereby prevent a negative impact on the silicon surface of a silicon substrate during plasma etching.
Yet another objective of the invention is to prevent a negative impact surface morphology of a silicon substrate during plasma etching.
Another objective of the invention is to monitor and thereby prevent a negative impact on the silicon surface of a silicon substrate during impurity implantations.
In accordance with the objectives of the invention a new method is provided for monitoring silicon quality, the new method is applied at the time of pre-salicidation of the silicon substrate. The optical refractive index of the pre-salicide substrate is monitored, this monitoring provides insight into the quality of the silicon substrate at that time of a substrate processing cycle.
REFERENCES:
patent: 4188123 (1980-02-01), Kleinknecht
patent: 5042952 (1991-08-01), Opsal et al.
patent: 5321264 (1994-06-01), Kuwabara et al.
patent: 5578161 (1996-11-01), Auda
patent: 6052185 (2000-04-01), Banet et al.
patent: 6141103 (2000-10-01), Pinaton et al.
patent: 6376343 (2002-04-01), Buynoski et al.
Lee Bih-Huey
Shen Yun-Hung
Barth Vincent P.
Rosenberger Richard A.
Taiwan Semiconductor Manufacturing Co. Ltd
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