Silicon building blocks in integrated circuit packaging

Details Silicon building blocks in integrated circuit packaging Silicon building blocks in integrated circuit packaging

2002-12-23

2004-11-09

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C136S201000, C438S745000, C438S753000

Reexamination Certificate

active

06815256

ABSTRACT:

BACKGROUND
As the speed and density of semiconductor integrated circuits increase, thermal and electrical connectivity issues have raised the requirements for packaging. Many integrated circuits are packaged using organic materials, materials and their processes not necessarily compatible with the expertise and capability of the semiconductor integrated circuit manufacturers. Some manufactures have taking to using a block of silicon between the integrated circuit die and the printed circuit board upon which it is to be mounted.
Generally, the integrated circuit die is mounted on the silicon building block, which in turn may be mounted on a plastic, or other material, substrate or package. This entire apparatus is then mounted on the printed circuit board. Mounting to the printed circuit board generally involves a ball grid array or pin grid array to complete the electrical connections between the integrated circuit and the printed circuit board.
The addition of silicon building blocks has loosened some of the manufacturing requirements of the package, reducing costs and making the packaging process less prohibitive to semiconductor manufacturers. However, the addition of the silicon building block has led to some problems such as large insertion loss, high return loss, cross talk and a high impedance path for power delivery. The silicon building block has high dielectric loss, resulting in large insertion loss. The return loss results from the impedance mismatch between the silicon building block and the die. Cross talk problems arise because of the higher order mode that propagates through the silicon building block. The small vias used for Vcc and Vss result in a high impedance path for power delivery.


REFERENCES:
patent: 3646666 (1972-03-01), Boleky et al.
patent: 4969022 (1990-11-01), Nishimoto et al.
patent: 5084403 (1992-01-01), Matsuoka
patent: 6608250 (2003-08-01), Ghoshal

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