Frequency compensation of common-mode feedback loops for...

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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Details

C330S259000, C330S292000

Reexamination Certificate

active

06774722

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to differential amplifiers, and more particularly, to frequency compensation of common-mode feedback circuits where the common-mode loop includes a number of gain stages.
BACKGROUND OF THE INVENTION
Operational amplifiers having a differential output require an accurate common-mode feedback loop in order to set the common-mode output voltage of the amplifier. The basic principle of operation for a common-mode feedback circuit is that the common-mode voltage is sensed and compared to a reference thereby generating a difference or “error” signal. The error signal is fed back into the main amplifier, and the common-mode of the amplifier is set equal to the reference voltage. The error is therefore eliminated.
In a typical common-mode feedback circuit, the common-mode voltage is sensed and compared to a reference by a differential pair. The resulting common-mode error signal is fed back to the operational amplifier by means of a current mirror. Often this conventional common-mode feedback implementation does not have enough gain, particularly in sub-micron processes. Thus, in the case of such processes, a common-source gain stage can be added.
This type of configuration, however, is associated with problems relevant to frequency compensation. For example, the loop is compensated by introducing a zero in the loop transfer function at the gate of the common-source gain stage. The capacitor of the zero is physically large, and therefore occupies a large die area. In addition, the bandwidth of the loop is considerably decreased due to the zero.
What is needed, therefore, are improved techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers.
BRIEF SUMMARY OF THE INVENTION
One embodiment of the present invention provides a circuit for performing frequency compensation of a common-mode feedback loop for a differential amplifier. The circuit comprises a sensing network operatively coupled to a differential output of the differential amplifier, for sensing a common-mode voltage output by the differential amplifier. A comparing network (e.g., a differential pair) is operatively coupled to the sensing network, and adapted to compare the sensed common-mode voltage to a reference and generate an error signal. A current inverter is operatively coupled to the differential sensing circuit for inverting the error signal. A gain stage is operatively coupled to the current inverter and the differential amplifier for providing a gain adjusted error signal to the differential amplifier. A pole-split network (e.g., a capacitor) is operatively coupled in parallel with the comparing network for compensating the frequency characteristic of the feedback loop.
Another embodiment of the present invention provides a method for performing frequency compensation of a common-mode feedback loop for a differential amplifier. The method comprises sensing a common-mode voltage output by a differential amplifier using a sensing network, comparing the sensed common-mode voltage with a reference to provide a common-mode error signal to the differential amplifier via a feedback path including a gain stage, and compensating for changes in the frequency characteristic of the common-mode feedback loop due to the gain stage using a pole-split network.
The present invention provides an improvement over conventional common-mode feedback loops for differential amplifiers that use pole-zero cancellation techniques by including a pole-split network in the common-mode feedback loop. The pole-split network enables the use of smaller capacitors in the circuit design, resulting in a robust design that is tolerant to parameter variations and also allows the common-mode feedback loop to have a high bandwidth.
The features and advantages described herein are not all-inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the figures and description. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and not to limit the scope of the inventive subject matter.


REFERENCES:
patent: 5008632 (1991-04-01), Sutterlin

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