Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2003-01-13
2004-02-17
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S052000, C365S069000, C365S072000, C324S755090, C714S042000, C714S718000, C714S719000
Reexamination Certificate
active
06693816
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory module sockets used to interconnect memory modules with other computer components. More specifically, the present invention relates to a memory module socket which has a reversed pinout configuration and which is particularly suitable for memory device testing.
2. State of the Art
Semiconductor integrated circuit devices are manufactured on wafers or other substrates of semiconductor material. Conventionally, many devices are manufactured on a single wafer and individual devices or groups of devices are singulated, or cut, from the wafer and packaged. The devices are tested at various points during the manufacturing process, e.g., while they are still in the wafer form, in die form (after singulation but prior to packaging), and after packaging.
Testing may be directed towards detection of flaws or errors regarding one or more facets of semiconductor fabrication. For example, one stage of testing concerns the physical structure of the device. Such testing may include the use of various techniques known in the art such as emission microscopes or X-ray analysis. Testing of the structure typically focuses on whether discernible errors or flaws developed during the physical formation of the semiconductor die. Such flaws may be the result of one or more processing steps improperly performed, such as, for example, over-etching. Flaws are also developed as a result of contaminants introduced during the fabrication process. Indeed, numerous factors exist which may influence the introduction and development of such flaws or errors.
Another facet of testing concerns the functionality and performance of the device. This typically involves connecting the device to a circuit such that a signal or combination of signals may be passed through the device. The response by the device to the signal is then monitored, with the output value being compared to values expected to be obtained from a properly functioning device. Tests may involve a particular signal or combination of signals being delivered repetitively, perhaps under extreme environmental or operational conditions (temperature, voltage, etc.) outside of normal parameters in order to identify a device which would fail after a shorter-than-usual period of use. Other tests may involve a number of different signals or signal combinations delivered in sequence. One method for testing a memory device is to deliver the same signal or signal combination to multiple identical subsections of the device simultaneously and compare the values read from the subsections (“compression testing”). If all of the respective read values match, the test has been passed, while a mismatch between respective values read from any of the subsections indicates a device malfunction and failure of the test.
Another stage of testing may concern the compatibility of the semiconductor device with other components. For example, it becomes desirable to confirm the compatibility of a memory device having a specific design with the multitude of personal computer motherboards currently available on the market. Such testing would involve connecting identical memory modules to motherboards of different design and manufacturing origin and then subjecting the memory modules to an otherwise identical testing process. This type of testing helps to assure computer manufacturers as well as consumers that the device will function as expected regardless of who may be the manufacturer of other interconnected components.
The ultimate objective of testing is to produce a device having verified reliability and quality. While this objective is of extreme importance, the efficiency with which testing is performed is also an important concern. It becomes desirable to reduce testing time whenever possible without compromising the integrity of the testing process. A reduction in test time, without a sacrifice in quality, results in greater manufacturing throughput and thus lowers manufacturing costs. Reduced manufacturing costs are very desirable in that they ultimately lead to higher profits for the company, as well as a savings to the consumer.
One method of reducing testing time without compromising the integrity of the testing process is to perform batch tests. In other words, numerous devices are tested coterminously instead of testing each device sequentially, one at a time. An example of such testing, with regards to memory devices, can be better understood with reference to
FIG. 1. A
testing apparatus
10
may include a plurality of motherboards
12
housed in a holding device such as a cabinet or a frame
14
. A plurality of memory devices, such as dynamic random access memory (DRAM) or other memory modules
16
, is appropriately coupled to individual memory sockets
18
. Each memory socket
18
is operatively coupled to a motherboard
12
with each motherboard
12
including multiple memory sockets
18
. Thus, each motherboard
12
is capable of accommodating several memory modules
16
during a given testing operation.
It is noted that the testing apparatus
10
is illustrated as holding identical motherboards. However, as noted above, such a testing apparatus
10
may accommodate various motherboard styles, designs, and sizes. Thus, the system as described may be employed in various facets of testing, including compatibility testing.
With the memory modules
16
in place, functional testing or, alternatively, compatibility testing of the memory modules
16
is conducted. As described above, the motherboards
12
provide a signal, or signals, to the memory modules
16
and then monitor the responsive output of each memory module
16
. The configuration as described above allows numerous memory modules
16
to be tested in a relatively short amount of time. However, while the above-described system allows for a greater quantity of devices to be tested at a given time, the turnaround time in removing tested modules and subsequent installation of untested modules is less than optimal.
One problem with a testing apparatus configuration such as is illustrated in
FIG. 1
is that, in an effort to maximize the number of memory modules
16
being tested at a given time, the ability to remove and replace the memory modules
16
becomes compromised. This essentially results from the density and close proximity of the motherboards
12
within the cabinet or frame
14
combined with the configuration and orientation of the memory sockets
18
on the motherboard
12
. A typical motherboard
12
is configured such that the memory sockets
18
are mounted along a planar surface of the motherboard
12
so that memory modules
16
respectively inserted therein extend transversely away from the motherboard
12
. Furthermore, the memory sockets
18
are typically fixed in their locations by mechanical means including soldering, riveting and other techniques known in the art. Therefore, to extract a memory module
16
from a memory socket
18
, it must be withdrawn from memory socket
18
in a direction perpendicular to the planar surface of the motherboard
12
. However, in a testing apparatus
10
where the motherboards
12
are configured in close vertical proximity to each other, removal of the memory module
16
becomes rather difficult and time consuming.
For example, still referring to
FIG. 1
, distance ‘A’ represents the distance between the top of a memory module
16
and an adjacent motherboard
12
. Distance ‘B’, on the other hand, represents the minimum distance that the memory module
16
must travel in order to be removed from the memory socket
18
(i.e., the distance required for the bottom of the memory module
16
to clear the top of the memory socket
18
). It may often be the case that distance ‘B’ is greater than distance ‘A’. In such a case, it becomes physically impossible to remove the memory modules
16
(or insert them) unless the motherboards
12
are first removed from the frame
14
. In the instance of a cabinet or frame
14
holding a plurality of motherboards
12
Brunelle Steven J.
Momenpour Saeed
Micro)n Technology, Inc.
Nguyen Viet Q.
TraskBritt
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