Polycide gate MOSFET process for integrated circuits

Details Polycide gate MOSFET process for integrated circuits Polycide gate MOSFET process for integrated circuits

1990-08-28

1992-07-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437192, 437193, 437200, 148DIG147, H01L 21265

Patent

active

051302667

ABSTRACT:
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

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