CMOS buffer circuit

Details CMOS buffer circuit CMOS buffer circuit

2002-11-06

2004-08-31

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S262000

Reexamination Certificate

active

06784701

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS buffer circuit that is appropriate for, for example, the internal circuit of a portable, battery-operated electronic device operated by the application of a comparatively low voltage in an environment wherein the ambient temperature changes greatly.
2. Description of the Prior Art
In the conventional design for a CMOS buffer circuit, two CMOS inverters having the same structure are connected in series. For this design, the transmission characteristics, which represent the relationship between the gate voltage and the drain current of the MOSFET of which each CMOS inverter is constituted, include: a negative temperature characteristic, according to which, in the area wherein the drain current is higher than at a point Q whereat the temperature coefficient of the drain current is “0”, the drain current, correlated with a fixed gate voltage, is reduced as the temperature rises; and a positive temperature characteristic, according to which, in the area wherein the drain current is lower than at the point Q, the drain current, correlated with a fixed gate voltage, is increased as the temperature rises. The power voltage and the voltage for a digital signal that are transmitted to the conventional CMOS buffer circuit are so set that the MOSFETs are operated in the area for the negative temperature characteristic.
This type of CMOS buffer circuit comprises, for example, inverters
10
and
20
, as is shown in FIG.
7
. The inverter
10
includes a p-channel MOSFET (hereinafter referred to as a “pMOS”)
11
and an n-channel MOSFET (hereinafter referred to as an “nMOS”)
12
. Similarly, the inverter
20
includes a pMOS
21
and an nMOS
22
. A power voltage Vdd and the voltage for a digital signal in are set so that each MOSFET performs an operation in the area for the negative temperature characteristic. If, for example, the power voltage Vdd is 5 V, when the level is high (hereinafter referred to as “H”) the voltage for the digital signal in is equal to or higher than 3.6 V, while when the level is low (hereinafter referred to as “L”) the voltage for the digital signal in is equal to or lower than 0.8 V.
In this CMOS buffer circuit, based on the digital signal in, the pMOS
11
and the nMOS
12
are complementarily turned ON/OFF and the inverter
10
outputs an inverted signal A
1
, following which, based on the inverted signal A
1
, the pMOS
21
and the nMOS
22
are complementarily turned ON/OFF and the inverter
20
outputs an inverted signal B
2
.
However, the conventional CMOS buffer circuit has the following problems.
As is shown in
FIG. 8
, since for a MOSFET a threshold voltage Vt tends to be high at a high temperature or to be low at a low temperature, while a drain current Ids tends to be low at a high temperature or to be high at a low temperature, the point Q is present in the transmission characteristic that represents the relationship between the gate-source voltage and the drain current. This is called a “temperature characteristic inversion phenomenon”. Further, conventionally, the power voltage Vdd is comparatively high, and as indicated by a characteristic line A in
FIG. 9
, a delay time tpd, i.e., a period extending from the time whereat a voltage is applied to the gate to the time whereat the drain current has risen to 10% of the maximum value, at a high temperature is greater than a delay time tpd at a low temperature.
Recently, however, CMOS buffer circuits have frequently been employed as internal circuits for battery-operated portable electronic devices, and for such circuits, the power voltage Vdd settings tend to be higher than the conventional ones. Therefore, since the voltage value used as a logical threshold value approaches a gate voltage Vgs at the point Q, the effect due to the temperature characteristic inversion phenomenon is remarkable, and as is indicated by a characteristic line B in
FIG. 9
, a delay time tpd inversion phenomenon may occur, i.e., the delay time tpd at a high temperature may be shorter than the delay time tpd at a low temperature. In this case, a great error occurs between the actual transmission delay time and a transmission delay time that is calculated by using a library (a set of various parameters, provided by a semiconductor manufacturing company, related to the CMOS buffer circuit). For example, the maximum value for the transmission delay time may be less than the minimum value, and the accuracy of the delay data may be reduced.
BRIEF SUMMARY OF THE INVENTION
SUMMARY OF THE INVENTION
According to the present invention, a CMOS buffer circuit comprises:
a first CMOS inverter for inverting an input digital signal and for outputting the resultant signal as a first inverted signal;
a second CMOS inverter for inverting the first inverted signal and for outputting the resultant signal as a second inverted signal; and
a delay circuit, having a transmission delay time that becomes longer as the temperature rises, for outputting to the second inverter, following a delay equivalent to the transmission delay time, the first inverted signal received from the first inverter,
wherein the first CMOS inverter includes
a first p-channel MOSFET, which has a first threshold value that becomes smaller as the temperature rises and which is rendered ON when a digital signal exceeds the first threshold value, and
a first n-channel MOSFET, having a second threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the first p-channel MOSFET, when a digital signal exceeds the second threshold value, and
wherein the second CMOS inverter includes
a second p-channel MOSFET, which has a third threshold value that becomes smaller as the temperature rises and which is rendered ON when the first inverted signal exceeds the third threshold value, and
a second n-channel MOSFET, having a fourth threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the second p-channel MOSFET, when the first inverted signal exceeds the fourth threshold value.


REFERENCES:
patent: 6525583 (2003-02-01), Huber

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