Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-11-19
2004-08-10
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S203000, C365S233100
Reexamination Certificate
active
06775201
ABSTRACT:
TECHNICAL FIELD
A method and an apparatus for outputting burst read data in a synchronous memory device are disclosed, and more particularly, a burst read data output method and apparatus are disclosed for effectively outputting a plurality of pre-fetched data bits at high speed.
DESCRIPTION OF THE RELATED ART
According to a conventional read operation at burst read mode in a synchronous memory device, some date bit cells are in sequence accessed according to inputted addresses in response to one read command. For example, if a burst length is 8, 8 bit data are outputted from the cells indicated by the inputted addresses into an output terminal DQ
In case of double data rate memory DRAM, data of 2 bits are internally pre-fetched at one time. When a burst length is 8, 4 times successive operations of accessing the data bit cell are required for the purpose of outputting 8 bit data into the output terminal DQ.
Recently, as the memory is highly speeded-up, the number of pre-fetched bits should be increased and moreover the pre-fetched data should be read at one time at higher speed in order to continuously output data of 8 bits into output terminal.
SUMMARY OF THE DISCLOSURE
There is a need for a method and apparatus for high speed outputting burst read data which are read and pre-fetched at one time.
A disclosed method for outputting burst read data from a synchronous memory, comprising: dividing some bit of burst read data outputted from the synchronous memory into an odd number data group and an even number data group; selecting a data bit which should be first outputted, and determining a data group including the selected data bit among the odd number data group and the even number data group; serially-outputting the determined data group at rising edges of the inputted clock signal; serially-outputting the undetermined data group at falling edges of the inputted clock signal; and multiplexing the serially-outputted determined data group and the serially-outputted undetermined data group at rising and falling edges of the inputted clock signal.
There is also provided an apparatus for outputting burst read data outputted from a synchronous memory, comprising: a data group selecting unit for dividing some bit of burst read data outputted from the synchronous memory into an odd number data group and an even number data group, and selecting a data bit which should be first outputted, and then determining a data group including the data bit among divided odd and even number data groups, and finally outputting the determined data group into a first path and the other data group into a second path; an output sequence control unit for outputting an output sequence control signal in order to determine output sequence of the data in the first and the second paths, based on the least significant bit of a column address and a mode control signal set in a mode register set; and an output sequence combining unit for combining data of the first path with that of the second path based on the output sequence control signal and synchronizing the combined data at rising and falling edges of an inputted clock signal, respectively, to output the synchronized data continuously.
REFERENCES:
patent: 6212111 (2001-04-01), Wright et al.
patent: 6438063 (2002-08-01), Lee
Kwak Jong Tae
Lee Seong Hoon
Hynix / Semiconductor Inc.
Le Vu A.
Marshall & Gerstein & Borun LLP
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