Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-06-06
2004-06-29
Yao, Kwang Bin (Department: 2667)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S413000
Reexamination Certificate
active
06757288
ABSTRACT:
The significance of transmission and switching technologies for high data transmission rates (greater than 100 Mbit/s) is increasing due to the increasing need for a transmission of video information in modern communications technology such as, for example, still and moving images in picture telephony applications or the display of high-resolution graphics at modem personal computers. The asynchronous transfer mode (ATM) is a known data transmission method for high data rates. A data transmission on the basis of the asynchronous transfer mode currently enables a variable transmission bit rate of up to 622 Mbit/s.
Known switching equipment, including those on the basis of the asynchronous transfer mode, are usually modularly constructed. A plurality of assemblies that, for example, realize an interface for the connection of subscriber lines, a central controller or a through-connection means can thereby usually be plugged onto a central plug assembly shared by all assemblies, what are referred to as a backplane, and are connected to one another thereover. The modularity of the switching equipment that is thereby achieved enables, among other things, an easy adaptation of a switching equipment to different configurations as well as a simplified error analysis when performing service [sic].
The data sheet “MPC860SAR—Functional Design Specification”, Motorola, 6/97 discloses a control module MPC860SAR that comprises an 8-bit wide, bidirectional ATM-specific bus interface (UTOPIA interface: Universal Test & Operations PHY Interface for ATM), for example for a connection of an assembly to an ATM switching equipment. The known control module controls a data transfer that can be realized via a connectable data bus, i.e. this control module is a “master” module for the 8-bit wide data bus that can be connected to it.
The data sheet “ICs for Communication—PBX 4240”, Siemens AG, 10/96, Order No. T4240-XV12-P1-7600, discloses a control module PXB 4240 that comprises two 8-bit wide, unidirectional ATM-specific bus interfaces (UTOPIA interfaces) and an STM-1 interface (Synchronous Transfer Mode with a transmission bit rate of 155 Mbit/s), for example for a connection of an optical fiber line. A conversion of an ATM data stream onto an STM data stream and vice versa can be realized with this module. This control module is thereby controlled by a data transfer implemented via one of the 8-bit wide data busses (UTOPIA interface), i.e. this control module is a “slave” module for the 8-bit wide data busses connectable to it.
EP 0 492 440 A1 discloses an ATM interface device via which a data communication between two ATM devices is realized upon intermediate storage of the communicated data in an FIFO memory (First In First Out). An inscription or, respectively, readout of data from the FIFO memory ensues with an activation of the FIFO memory by a read or, respectively, write signal sent from an ATM device.
The present invention is based on the object of specifying a method and an arrangement for a data transmission between a first ATM device configured as “master” and a second ATM device configured as “slave” with which differing data processing capacities of the first and of the second ATM device are compensated.
This object is inventively achieved with the features of patent claim
1
and
2
or, respectively,
7
.
A time decoupling of the first data bus from the second data bus is realized by an interposition of an ATM interface device that is connected via a first data bus to the first ATM device and via a second data bus to the second ATM device, so that the first and the second data bus can be operated with a separate clock rate different from one another.
Fluctuations in the data transmission rate, which are particularly caused by the ATM communication technology, can be compensated by an intermediate storage of data to be communicated between the first and the second ATM device.
A further advantage of the invention is comprised therein that the ATM interface device can be realized both with a minimal HW outlay as well as with a simple software for the control of the data transfer.
REFERENCES:
patent: 5222108 (1993-06-01), Suzuki
patent: 5548587 (1996-08-01), Bailey et al.
patent: 5991295 (1999-11-01), Tout et al.
patent: 0 492 440 (1992-07-01), None
Siemens, Semiconductor Group, “ICs for Communications”, Synchronous Digital Hierarchy Transceiver, PXB 4240, Oct. 1996, Order No. T4240-XV12-P1-7600, Version 1.2, 4 pages.
Data Sheet: MPC860SAR—“Functional Design Specification”, Motorola, Jun. 1997, 3 pages.
Boll Gunnar
Deml Reinhard
Siemens Aktiengesellschaft
Staas & Halsey , LLP
Yao Kwang Bin
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