Synchronous mirror delay (SMD) circuit and method including...

Details Synchronous mirror delay (SMD) circuit and method including... Synchronous mirror delay (SMD) circuit and method including...

2004-01-13

2004-11-02

Tokar, Michael (Department: 2819)

Oscillators

Ring oscillators

C331S046000, C327S161000, C327S276000

Reexamination Certificate

active

06812799

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically to synchronizing internal clocking signals generated in an integrated circuit with external clocking signals applied to the integrated circuit.
BACKGROUND OF THE INVENTION
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), measure controlled delays (MCDs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are nominally coincident and signals that have a desired delay relative to one another.
FIG. 1
is a functional block diagram of a conventional SMD
100
that receives an applied clock signal CLK and generates a synchronized clock signal CLKSYNC in response to the CLK signal, the CLKSYNC being synchronized with the CLK signal. The SMD
100
includes an input buffer
102
that receives the CLK and generates a buffered clock signal CLKBUF in response to the CLK signal. The CLKBUF signal has a delay D
1
relative to the CLK signal, where D
1
corresponds to the inherent propagation delay of the input buffer.
A model delay line
104
receives the CLKBUF signal and generates a forward delay clock signal FDCLK having a model delay D
1
+D
2
relative to the CLKBUF signal. The model delays D
1
and D
2
simulate the delay D
1
introduced by the input buffer
102
and a delay D
2
introduced by an output buffer
106
that generates the CLKSYNC signal, as will be explained in more detail below. The FDCLK signal propagates through a forward delay line
108
including a plurality of unit delays
11
A-N coupled in series, each unit delay receiving an input signal from the prior unit delay and generating an output signal having a unit delay UD relative to the input signal. Each unit delay
110
A-N may, for example, be an AND gate having one input enabled as indicated for the unit delay
110
A, with the inverter introducing the unit delay UD corresponding to the propagation delay of the inverter. In the forward delay line
104
, the FDCLK signal propagates through the unit delays
110
A-N from left to right in
FIG. 1
, as indicated by the orientation of the inverter in the unit delay
110
A. The forward delay line
108
includes a plurality of outputs
112
A-N, each output
112
A-N being coupled to the output from the corresponding unit delay
110
A-N, respectively. As the FDCLK signal propagates through the unit delays
110
A-N, when the signal is present on a respective output
112
A-N the signal is designated a delayed forward clock signal DFDCLK.
A backward delay line
114
includes a plurality of unit delays
116
A-N coupled in series as previously described for the forward delay line
108
. Instead of providing the outputs from the unit delays
116
A-N as with the forward delay line
108
, however, the backward delay line
114
has a plurality of inputs
118
A-N, each input being coupled to the input of the corresponding unit delay
116
A-N, respectively. Once again, each unit delay
116
A-N may be formed by an AND gate having one input coupled to the corresponding input
118
A-N. A mirror controller
120
is coupled to the outputs
112
A-N of the forward delay line
108
and the inputs
118
A-N of the backward delay line
114
. In response to rising-edges of the CLKBUF signal, the mirror controller
120
applies the DFDCLK signal from the corresponding unit delay
110
A-N in the forward delay line
108
to the input of the corresponding unit delay
116
A-N in the backward delay line
114
. For example, if the FDCLK signal has propagated to the output of the unit delay
110
J, the mirror controller
120
outputs the DFDCLK signal on the output of the unit delay
110
J to the input of the unit delay
116
J in the backward delay line
114
. The unit delays
116
A to
116
I and
116
K to
116
N are unaffected. The DFDCLK signal propagates through the corresponding unit delay
116
J in the backward delay line
114
and through all unit delays
116
I-A to the left of that unit delay, and is output from the backward delay line
114
as a delayed clock signal CLKDEL. Thus, in the backward delay line
114
, DFDCLK signal propagates through the unit delays
116
A-N from right to left in
FIG. 1
, as indicated by the orientation of the AND gate in the unit delay
116
A. The output buffer
106
receives the CLKDEL signal and generates the CLKSYNC in response to the CLKDEL signal, with the CLKSYNC being delayed by the delay D
2
introduced by the output buffer.
The overall operation of the SMD
100
in synchronizing the CLKSYNC signal with the CLK signal will now be described in more detail with reference to
FIG. 1 and a
signal timing diagram of
FIG. 2
illustrating various signals generated by the SMD during operation. In the example of
FIG. 2
, an initial rising-edge of the CLK signal occurs at a time T
0
. In response to the rising-edge of the CLK signal at the time T
0
, the input buffer
102
drives the CLKBUF signal high the delay D
1
later at a time T
1
, with this initial rising-edge of t

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