Programmable delay for processor control signals

Details Programmable delay for processor control signals Programmable delay for processor control signals

2002-04-17

2004-08-03

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S263000

Reexamination Certificate

active

06771106

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to processors, and, more particularly, to an programmable delay for processor control signals.
BACKGROUND OF THE INVENTION
Conventional computer systems include a processor coupled to a variety of memory devices, including read-only memories (ROMs) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (SRAM). The processor also communicates with external peripheral devices such as input devices, output devices and data storage devices using control signals. As shown in
FIG. 1
, common output driver circuit
10
embedded within the processor circuit includes a n-type and p-type transistor
12
and
14
coupled to provide a push-pull arrangement.
Processors generally operate at relatively high speeds. Processors such as the Pentium IV are currently available that operate at clock speeds of at least 1.5 GHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency.
Currently, for example, a processor having a 1.5 GHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components. The time required for the processor, operating, for example, at 1.5 GHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
Access to system memory is a frequent operation for the processor. In operation, processors access external memory devices in time periods that are multiples of the processor master input clock. Since these devices do not operate at the clock speed of the mother board, access often requires that wait states be generated to halt the processor until the external device has completed the memory transfer. If external memory accesses take ‘n’ clock cycles, this is known as a “zero wait state access”. If, however, the processor is faster than the external memory device, extra wait states are added per access to accommodate for the external memory's timing requirements. In many high performance designs, situations arise in which an extra wait state must be added simply because a setup-time or hold-time requirement is missed by one or two nanoseconds.
Specifically, the processor operates on a master input clock and all of its output and input signals references this master input clock. When the processor accesses the external memory device, control signals are activated relative to the master input clock signal. If the memory device does not respond with valid sampled data, the processor must retrieve the memory data on the next clock edge. Thus, given a 100 MHz processor, if the processor misses the timing requirements even by one nano-second, it must wait another clock period or 10 nano-seconds, in this example, before it can sample the data again. In systems having a 10 nanosecond SRAM where memory is accessed in two clock cycles, data may be retrieved every 20 nanoseconds but if a timing requirement is missed, the processor must wait another 10 nanoseconds which degrades performance by 30%.
Typically, adding wait states in multiples of processor master input clock periods has been the only way to satisfy timing requirements when peripheral device timing requirements do not exactly match the processor control timing. As a result, the designer of the system is forced to make a significant reduction of the memory access bandwidth in order to meet the timing requirements of the memory device. For example, if a zero wait state access to a memory device takes two processor clock cycles, having to add one wait state due to a missed setup time by one nanosecond reduces the bandwidth up to 50%. This is a huge penalty for high performance systems. Thus, adding wait states to high speed, high performance systems can dramatically reduce the performance of the system.
An approach as disclosed in U.S. Pat. No. 6,178,488, which is incorporated by reference herein, includes the use of a multiplexer that sequentially applies each of the 16-bit data words to a read FIFO buffer. Successive 16-bit data words are clocked through the FIFO buffer by a clock signal generated from an internal clock by a programmable delay circuit. This programmable delay circuit, however, is a synchronous circuit in which processes are delayed by a programmable number of clock periods. Similarly, this separate resultant internal clock generated by the delay circuit has a clock period greater than the master input clock, equal to some multiple of the master input clock. The minimum delay that this circuit can introduce is one clock period of the master input clock. Thus, the problem still remains where there is a need to extend a control signal by an interval that is less than one clock period, instead of the typical method of delaying signals in multiples of the master input clock period.
With the increasing demand for faster processor speeds, maximum processor bandwidth for external peripherals, and maximum processor performance, there is a need for a finer granularity of the control signal timing of the processor such that wait state additions are eliminated as the only means of satisfying timing requirements. Thus, there is a need for a programmable delay driver circuit at the control signal output of a processor that can add a predetermined delay which is less than the master input clock period.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the (processor control signal timing), the present invention teaches programmable delay circuit for control signals that maximize processor bandwidth to external peripherals by eliminating wait state addition as the only means to satisfy timing requirements. A first embodiment may include a programmable delay chain connected to a hysteresis circuit. A processor control signal is fed into the programmable delay chain which includes at least one switch and at least one resistive element connected together. A first feedback circuit connects the output of the programmable delay chain to the input of the first embodiment to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit which provides a stable signal connects to an output driver for driving the processor control signal.
Alternatively, other embodiments may include substitutes for the resistive elements and switches.


REFERENCES:
patent: 6166971 (2000-12-01), Tamura et al.
patent: 6178488 (2001-01-01), Manning
patent: 6229364 (2001-05-01), Dortu et al.
patent: 6377093 (2002-04-01), Lee et al.

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