Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2003-06-12
2004-11-16
Gushi, Ross (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C409S066000, C409S075000
Reexamination Certificate
active
06817870
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to connecting multiple circuit boards and, more particularly, to a technique for interconnecting two or more multilayer circuit boards having vias of varying depths.
BACKGROUND OF THE INVENTION
The limitations inherent to single signal layer printed circuit boards (PCBs) led to the development of multilayer PCBs. Such multilayer PCBs may be either single or double-sided and may have multiple signal layers on the surface of and buried within the multilayer PCBs.
While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components. For example, when making electrical connections between different layers in multilayer PCBs, electrically conductive vias generally are used. While these electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB, there are intrinsic parasitics associated with these electrically conductive vias that can adversely affect the performance of signals propagating therethrough. That is, these electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance that can adversely affect signals propagating along each electrically conductive via. In addition, these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof. Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via. These adverse affects only increase as the number of layers in a multilayer PCB increase.
In recognition of the increase in adverse effects on signal integrity as the layer count of a PCB increases, techniques have been developed to provide for “channel routing” within a PCB to reduce the number of layers necessary to provide the requisite electrical connections. An exemplary channel routing technique is described in U.S. Pat. No. 6,388,890 issued on May 14, 2002 to Kwong et al., the entirety of which is hereby incorporated by reference herein. Kwong et al. disclose a technique for manufacturing and using a PCB wherein certain vias extend only through a subset of the layers of the PCB to create channels in the portions of the PCB where vias are absent. These channels then may be used to route a larger number of signal, power, ground and/or test traces between vias thereby reducing the number of layers necessary to provide a certain number of electrical connections.
In addition to the development of channel routing to overcome the limitations posed by the increase in circuit complexity, techniques for interconnecting multiple circuit boards have been developed to provide additional functionality. For multiple PCB solutions, such as mother/daughter cards, passive connectors typically are used to provide electrical connections between the PCBs. While providing for the use of multiple interconnected PCBs in a circuit module, these passive connectors introduce a variety of problems to the operation of the circuit module. In many instances, these connectors introduce parasitic capacitance, parasitic resistance, parasitic inductance, electromagnetic interference (EMI), noise, increased power consumption, and the like, which typically result in attenuation of signals transmitted between the PCBs. Further, the implementation of connectors often significantly increases the cost of producing circuit modules having multiple interconnected PCBs. In addition, conventional interconnect techniques fail to take advantage of the benefits provided by circuit boards utilizing channel routing.
In view of the foregoing, it would be desirable to provide a technique for interconnecting multiple PCBs that overcomes the above-described inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for interconnecting circuit boards that implement channel routing.
SUMMARY OF THE INVENTION
A circuit device for interconnecting first and second multilayer circuit boards is provided in accordance with one embodiment of the present invention. The first multilayer circuit board has a first plurality of electrically conductive vias of varying depths and the second multilayer circuit board has a second plurality of electrically conductive vias. The circuit device comprises a first plurality of pins located on a first side of the circuit device corresponding to the first plurality of electrically conductive vias of the first multilayer circuit board, each pin having a length compatible with a depth of a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board. The circuit device further comprises a second plurality of pins located on a second side of the circuit device corresponding to the second plurality of electrically conductive vias of the second multilayer circuit board.
A circuit module is provided in accordance with another embodiment of the present invention. The circuit module comprises a first multilayer circuit board having a first plurality of electrically conductive vias of varying depths and a second multilayer circuit board having a second plurality of electrically conductive vias. The circuit module further comprises a circuit device having a first side mounted to a surface of the first multilayer circuit board and a second side mounted to a surface of the second multilayer circuit board. The circuit device comprises a first plurality of pins located on the first side of the circuit device corresponding to the first plurality of electrically conductive vias of the first multilayer circuit board, each pin extending into and in electrical contact with a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board and a second plurality of pins located on the second side of the circuit device corresponding to the second plurality of vias of the second multilayer circuit board, each pin extending into and in electrical contact with a respective one of the second plurality of electrically conductive vias of the second multilayer circuit board, wherein each of the first plurality of pins of the circuit device has a length compatible with a depth of a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board.
A method for implementing a circuit device to interconnect at least first and second multilayer circuit boards is provided in accordance with another embodiment of the present invention. The circuit device includes a first plurality of pins located on a first surface of the circuit device and a second plurality of pins located on a second surface of the circuit device, the first multilayer circuit board includes a first plurality of electrically conductive vias of varying depths and the second multilayer circuit board having a second plurality of electrically conductive vias. The method comprising the step of forming at least one pin of the first plurality of pins of the circuit device to have a length compatible with a depth of a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board. The method further comprises the steps of joining the first surface of the circuit device to a surface of the first multilayer circuit board, each pin of the first plurality of pins extending into and being in electrical contact with a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board and joining the second surface of the circuit device to a surface of the second multilayer circuit board, each pin of the second plurality of pins extending into and being in electrical contact with a respective one of the second plurality of electrically conductive vias of the second multilayer circuit board.
The present
Difilippo Luigi
Kwong Herman
Wyrzykowska Aneta
Gushi Ross
Hunton & Williams LLP
Nortel Networks Limited
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