Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-03-26

2004-06-15

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230050

Reexamination Certificate

active

06751154

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, typified by dynamic random access memory (hereinafter abbreviated as DRAM) and the like.
2. Related Background Art
Conventionally, in a semiconductor memory device, especially in DRAM that has a memory cell configured with two transistors and one capacitor for the purpose of realizing a high-speed random operation by two-port accessing the two transistors in an interleave operation mode, addresses are decoded by means of an address latch circuit for latching an address signal, an address decode circuit for decoding an address, a circuit for conducting frequency-division of an address signal into two ports and a control signal for controlling these circuits. Because of this configuration, the conventional semiconductor memory device has a drawback of being incapable of realizing high-speed random accessing. The following describes the conventional semiconductor memory device in detail.
FIG. 14
is a block diagram showing a main configuration of the conventional semiconductor memory device. In
FIG. 14
, reference numerals
16
and
17
denote an A-port address latch circuit and a B-port address latch circuit, respectively, both of which are configured with: an address control circuit for switching between the fetching of an external address EXTADD and the fetching of a refresh address INTADD; and an address latch circuit for latching the thus fetched address signal.
Reference numeral
18
denotes a peripheral circuit including a circuit for generating a signal controlling these address latch circuits
16
and
17
, and
19
denotes a row decoder block that includes an A-port word driver and a B-port word driver for controlling two transistors to access a memory cell.
Reference numeral
9
denotes a command buffer,
10
denotes a command decoder for decoding a command and
11
denotes a frequency-division clock generation circuit for generating a frequency-division clock to control the timing of the decoding of a command.
FIG. 16
is a schematic diagram showing a memory cell and word drivers. In
FIG. 16
, reference numerals
24
and
25
denote an A-port access transistor and a B-port access transistor respectively. Reference numeral
26
denotes a memory cell capacitor. One terminal of the capacitor
26
is coupled to a cell plate voltage source VCP and the other terminal of the capacitor
26
is commonly coupled to source/drain terminals of the transistors
24
and
25
. The other terminals of the transistors
24
and
25
are coupled to an A-port bit line BLA and a B-port bit line BLB respectively. The gate terminals of the transistors
24
and
25
are coupled to an A-port word line WLA and a B-port word line WLB respectively. The transistors
24
and
25
, and the capacitor
26
form a memory cell MC. Only one memory cell is shown in the figure. A person skilled in the art, however, would understand that the memory cell MC is repeatedly arranged in rows and columns to form a memory cell array.
Reference numerals
22
and
23
denote an A-port word driver and a B-port word driver respectively. The A-port word driver
22
and the B-port word driver
23
drive an A-port word line WLA and a B-port word line WLB respectively. Only one A-port word driver
22
is shown in the figure. A person skilled in the art, however, would understand that the A-port word driver
22
is repeatedly arranged in the column direction. Similarly, it would be understood that the A-port word line WLA is repeatedly arranged in the column direction. Further, the B-port word driver
23
and the B-port word line WLB are also arranged repeatedly in the column direction.
An address decoding operation by the thus configured semiconductor memory device will be described below, with reference to a timing chart shown in FIG.
15
.
With reference to
FIG. 15
, firstly in cycle A, when a read operation (READ command) is carried out as an external access, an address signal A
0
input from an external input ADD is latched by a latch circuit in an address buffer
7
to be synchronized with an external clock signal CLK and is transferred to the A-port address latch circuit
16
as an internal address signal EXTADD
0
. During this procedure, the command READ input from an external input CMD is latched by the command buffer
9
to be synchronized with the external clock signal CLK and then is decoded into an internal signal by the command decoder
10
.
Then, using the thus decoded command signal and a frequency-division clock signal ACLK/BCLK generated from the external clock CLK by the frequency-division clock generation circuit
11
, a command control signal ACTA/ACTB subjected to the frequency-division is generated. This control signal ACTA/ACTB is used for conducting frequency-division of the internal address signal EXTADD
0
into an A-port address signal PDA in the A-port address latch circuit
16
, which is transferred to a row address decoder
20
.
Thereafter, the address signal PDA is rendered into an address decode signal PDDA by the row address decoder
20
. Then, the address decode signal PDDA activates a desired A-port word driver
22
and activates an A-port memory cell transistor to access a desired memory cell capacitor.
Next, the address in the cycle A is reset. More specifically, the address signal PDA and the address decode signal PDDA are reset by resetting the address buffer
7
and the A-port address latch circuit
16
after a period of the frequency-division has passed, so that the A-port word driver
22
is reset.
However, the above-stated configuration has the following problems: that is, when setting an address signal in the above device, the address buffer
7
firstly is used for latching the address signal according to the external clock signal CLK. In addition, according to the control signal ACTA/ACTB, which starts at a later timing than the external clock CLK, the address signal EXTADD is allocated into one of the latch circuits so as to be latched and then decoded. Due to this configuration, it takes a long time to set the address signal, so that the random access cannot be speeded up further.
Also, since the address signal is divided into two lines at the A-port address latch circuit
16
and the B-port address latch circuit
17
, two sets of circuits are required for the later stages also, which causes problems of an increase in circuit area and an increase in address bus that is arranged on the row decoder.
Moreover, the address signal is reset in such a manner that after the A-port address latch circuit
16
or the B-port address latch circuit
17
is reset, the row address decoders
20
and
21
are reset and the word drivers
22
and
23
are reset. Due to this configuration, it takes a long time to, in particular, pre-charge a long address decode signal PDDA/PDDB on the row address decoders, which hinders the speedup of the random cycle.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor memory device that can realize fast random access, while reducing a device area.
In order to fulfill the above-stated object, the semiconductor memory device according to the present invention includes: a memory cell including two transistors and one capacitor; two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell; two address latch circuits for latching a first address signal to select one of the word drivers, the two address latch circuits being respectively provided upstream from the two word drivers; and an address decoder for decoding a second address signal to generate the first address signal. The address decoder supplies the first address signal in common to both of the two address latch circuits.
With this configuration, the address is not latched until an external input is conducted and the address is decoded. That is to say, during a time period for generating a control signal for latching inside of the de

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