Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-11-05
2004-11-09
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000
Reexamination Certificate
active
06815829
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a semiconductor chip and an interposed substrate having outer connecting terminals.
2. Description of Related Art
In order to raise the substantial integration degree of a semiconductor device, a semiconductor device having so-called a chip-on-chip structure has been proposed. On the other hand, in order to reduce the mounting area of a semiconductor device on a mounting substrate, an IC package has been developed, which is so-called a chip size package.
FIG. 4
is a schematic sectional view showing an example of a semiconductor device having a chip-on-chip structure packaged in a chip size package. A pair of semiconductor chips constituting the chip-on-chip structure include a primary chip
1
having pads
11
for outer connection and a secondary chip
2
to be bonded to the primary chip
1
. The primary chip
1
and the secondary chip
2
are electrically and mechanically connected to each other by bumps
12
, with active surfaces thereof being opposed to each other. On the active surface of the primary chip
1
, pads
13
for outer connection are provided in the peripheral part away from the secondary chip
2
and are electrically connected through bonding wires
14
to an interposed substrate
3
called an interposer. The inert surface of the primary chip
1
is bonded onto a surface of the interposed substrate
3
, for example, with an adhesive, and thereby the chip-on-chip structure is fixed on the surface of the interposed substrate
3
.
On the interposed substrate
3
, a mold resin
5
is disposed. Within the mold resin
5
, the primary chip
1
, secondary chip
2
and the bonding wires
14
are sealed. On the lower surface of the interposed substrate
3
, which is the surface on the opposite side from the primary chip
1
, a plurality of solder balls
15
serving as outer connecting terminals are two-dimensionally disposed in a grid-like arrangement. The semiconductor device is bonded to a mounting substrate by means of the solder balls
15
.
FIG. 5
shows another example of a semiconductor device having a chip-on-chip structure. In this semiconductor device, the inert surface of a secondary chip
2
is bonded onto a primary chip
1
, for example, with an adhesive. The primary chip
1
and the secondary chip
2
are electrically connected to each other by means of bonding wires
17
.
A common problem of the structures shown in
FIGS. 4 and 5
is that the semiconductor chips are stacked and therefore the height of each package is large. This problem can be reduced to some extent by grinding the mold resin
5
e.g. using a grinder as shown with a two-dots-and-dash line in
FIG. 4
, but the thinning of the package is limited.
In the case of the structure of
FIG. 4
, such grinding does not have so large an influence on the electric property of the device, even if the mold resin
5
is ground till the inert surface of the secondary chip
2
is exposed. However, in order not to hurt the bonding wires
14
, such grinding of the mold resin
5
must be stopped at the time when the mold resin
5
still remains above the bonding wires
14
.
In the case of the structure of
FIG. 5
, since the bonding wires
17
also electrically connect the primary chip
1
and the secondary chip
2
to each other, grinding of the mold resin
5
must be further limited.
On the other hand, in the structure of
FIG. 4
, if the mold resin
5
is ground till the inert surface of the secondary chip
2
is exposed, heat of the secondary chip
2
can be well radiated. On the contrary, since the interposed substrate
3
is present between the primary chip
1
and the outer space, heat of the primary chip
1
cannot be easily radiated. Therefore, when an element generating a large amount of heat such as a driving transistor is contained in the primary chip
1
, such difficulty in heat radiation has a disadvantageous influence on not only the operational property of the primary chip
1
but also the property of the secondary chip
2
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a semiconductor chip bonded onto a surface of a solid device, and capable of effectively reducing the thickness thereof.
A semiconductor device according to the present invention comprises (i) a semiconductor chip, (ii) a solid device provided with a bonding surface including a chip bonding region for bonding the semiconductor chip thereon and an outer connecting portion provided outside the chip bonding portion, and (iii) an interposed substrate having a containing portion capable of containing the semiconductor chip, a connecting portion to be bonded with the outer connecting portion, the connecting portion being provided in a peripheral part of the containing portion on a first surface opposed to the bonding surface, and outer connecting terminals provided on a second surface on the opposite side of the first surface.
With this structure, the semiconductor chip is contained in the containing portion provided in the first surface of the interposed substrate. The solid device bonded to the semiconductor device in this state is electrically connected to the connecting portion of the interposed substrate through the outer connecting portion provided on the outer side of the chip bonding region. Thereby, since the semiconductor chip is contained with the use of the thickness of the interposed substrate, the whole thickness of the semiconductor device can be reduced.
Further, since the surface, on the opposite side from the bonding surface, of the solid device is not opposed to the interposed substrate, heat can be well radiated from this surface. By mounting a heat radiating plate on this surface at need, the heat radiating efficiency can be further increased.
The solid device may be another semiconductor chip or a wiring substrate. The containing portion may be a containing recess provided in the first surface of the interposed substrate or a through hole penetrating through the interposed substrate.
The semiconductor chip may be bonded to the surface of the solid device in the facedown posture with the active surface thereof being opposed to the surface of the solid device. Further, the semiconductor chip may be bonded to the surface of the solid device in the faceup posture with the inert surface thereof being opposed to the surface of the solid device.
In order to execute facedown bonding, the semiconductor device may be bonded to the solid device by providing bumps respectively on the active surface of the semiconductor device and the bonding surface of he solid device and then bonding the bumps together. Further, in order to execute faceup bonding, the active surface of the semiconductor device and the solid device may be electrically connected using bonding wires.
Since the interposed substrate has outer connecting terminals on the second surface thereof on the opposite side of the first surface, the semiconductor device can be mounted on a mounting substrate using the outer connecting terminals. In this case, the outer connecting terminals may be in a land grip array in which a plurality of conductor patterns are exposed in a grid like arrangement, or in a ball grid array in which conductive members such as solders are disposed respectively on the plurality of conductor patterns formed on the second surface.
The solid device and the interposed substrate are preferably bonded by wireless bonding which directly bonds the outer connecting portion of the solid device and the connecting portion on the first surface of the interposed substrate. In this case, both or either of the outer connecting portion and the connecting portion preferably comprises a bump.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6084308 (2000-07-01), Kelkar et al
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