Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-02-13
2004-02-17
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06693617
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a liquid crystal display apparatus and a data driver having a sampling pulse generating circuit that generates a plurality of sampling pulses for carrying out the sampling of an inputted signal in accordance with an inputted clock signal.
BACKGROUND OF THE INVENTION
FIG. 5
shows an example of a conventional driver monolithic-type liquid crystal display apparatus. As shown in
FIG. 5
, there are provided, on a transparent substrate such as a glass substrate and a quartz substrate, a data driver
101
, a gate driver
102
, and a display section
103
, thereby constituting a driver monolithic-type liquid crystal display apparatus.
To the data driver
101
, are inputted a start pulse sp (control signal), clock signals ck and ckb, and video signals
1
and
2
(image signals), respectively.
To the gate driver
102
, are inputted signals such as a start pulse spg and clock signals ckg and ckgb. The display section
103
is constituted by thin film transistors (TFT)
104
in a matrix manner. The gate terminals of the respective thin film transistors
104
, constituting the display section
103
, are connected to gate bus lines G
1
, G
2
, . . . , Gn that are extended from the respective outputs of the gate driver
102
. The source terminals of the respective thin film transistors
104
are connected to source bus lines {circle around (1)}, {circle around (2)}, . . . , n that are extended from the respective outputs of the data driver
101
. The drain terminals of the respective thin film transistors
104
are connected to pixel capacitors
105
(pixel capacity) formed by transparent electrodes and opposite electrodes.
As shown in
FIG. 6
, the data driver
101
is constituted by a sampling pulse generating circuit
201
and analog switches
202
for sampling the image signals (the video signals
1
and
2
(inputted signals)) that were inputted into the data driver
101
.
The sampling pulse generating circuit
201
, as shown in FIG.
7
(
a
), is constituted by (1) a shift register having a plurality of D-type flip-flops
301
that are cascade connected with each other and (2) AND circuits
302
for carrying out the operation of logical product with respect to the respective adjoining D-type flip-flops
301
. The adjoining outputs (adjoining two outputs among the outputs Q
1
through Q
5
in FIG.
7
(
a
)) of the respective stages of the shift register are inputted into the corresponding AND circuit
302
.
The following explanation deals with the operation of the conventional liquid crystal display apparatus. Upon receipt of the start pulse sp, and the clock signals ck and ckb, the sampling pulse generating circuit
201
, as shown in a timing chart of FIG.
7
(
b
), consecutively outputs the first stage output SAM
1
, the second stage output SAM
2
, the third stage output SAM
3
, . . . , respectively, these outputs being sampling pulses.
To the sampling pulse generating circuit
201
, at the timing shown in
FIG. 8
, are inputted the video signals
1
and
2
(image signals) that are the image signals obtained by being subject to time base extension in which the original image signals are twice time-base-extended. In accordance with the first stage output SAM
1
, the second stage output SAM
2
, the third stage output SAM
3
, . . . , the display image data are written into the source bus line capacitor through a sample hold circuit composed of the analog witches
202
and hold capacitor (capacity) formed by the source bus lines {circle around (1)}, {circle around (2)}, . . . , n that constitute the display section
103
.
While writing the display image data into the respective source bus lines {circle around (1)}, {circle around (2)}, . . . , n in accordance with the sampling pulses, i.e., the first stage output SAM
1
, the second stage output SAM
2
, the third stage output SAM
3
, . . . , the gate bus line Gn (the output of the gate driver) is active, thereby the data, written into the respective source bus lines {circle around (1)}, {circle around (2)}, . . . , n through the thin film transistors
104
that are connected to the gate bus line Gn, are consecutively stored into the pixel capacitors
105
constituting the display section
103
. Then, the sampling is finished with respect to the image data that correspond to the amount of one horizontal period. After having finished the writing of the data into the pixel capacitors
105
, the gate bus line Gn becomes non-active. Until the display image data that correspond to the amount of the next frame period, the image data, written into the pixel capacitors
105
, is maintained, thereby carrying out the image display of the liquid crystal display apparatus.
When carrying out the sampling of the image data in accordance with the foregoing operations, the actual sampling pulses outputted from the sampling pulse generating circuit
201
(for example, in the case of
FIG. 6
, the sampling pulses correspond to the first stage output SAM
1
, the second stage output SAM
2
, the third stage output SAM
3
, and the fourth stage output SAM
4
) have blunt wave forms, as shown in
FIG. 9
, due to additional capacity such as gate capacity of the analog switch
202
to be driven. When the sampling pulse becomes blunt, there occurs time Tob during which the n-th stage output SAMn overlaps with the (n+1)-th stage output SAMn+1.
In the case where the sampling of the image data is carried out, the data at the time when the sampling pulse turns off is written into the hold capacitor (in the case of the liquid crystal display apparatus, the hold capacitor correspond to the capacitor formed by the source bus lines). At this time, prior to the time Tob just before the n-th stage output SAMn perfectly turns off, the (n+1)-th stage output SAMn+1 turns on, thereby causing a noise in the image data to occur due to the charging and discharging of the source bus line capacitor. This results in that the appropriate sampling of the image data can not be carried out.
In order to overcome the foregoing problem, the following arrangement is proposed (see FIG.
10
). As shown in
FIG. 10
, the logical product operation is carried out by an AND circuit
603
with respect to each stage output of the sampling pulse generating circuit
201
and a signal that is obtained by delaying the above-mentioned each stage output so as to narrow the pulse width of each stage output. More specifically, the n-th stage AND circuit
603
carries out the logical product operation with respect to the n-th stage output SAMn and a signal outputted from the n-th stage delay circuit
602
delaying the n-th stage output SAMn so as to narrow the pulse width of the n-th stage output SAMn.
With the foregoing arrangement, as shown in
FIG. 11
after the n-th stage AND circuit
603
carries out the logical product operation with respect to the n-th stage output SAMn and the delayed signal SAMdn outputted from the n-th stage delay circuit
602
, the resultant signal SAMn′ thus subject to the logical product operation is outputted as the n-th stage output from the sampling pulse generating circuit
201
. Similarly, after the (n+1)-th stage AND circuit
603
carries out the logical product operation with respect to the (n+1)-th stage output SAMn+1 and the delayed signal SAMdn+1′ outputted from the (n+1)-th stage delay circuit
602
, the resultant signal SAMn+1′ thus subject to the logical product operation is outputted as the (n+1)-th stage output from the sampling pulse generating circuit
201
.
Since the time duration (Td
1
through Td
4
in
FIG. 11
) is provided for each stage output (sampling pulse), it is avoidable that the adjoining outputs SAMn′ and SAMn+1′ overlap with each other, thereby reducing the noise occurred in the image data.
As shown in
FIG. 12
, another conventional arrangement is proposed so as to narrow the pulse width of the sampling pulse (see the timing chart of FIG.
13
), in which a delay circuit
803
for delaying the clock sign
Kumada Kouji
Sasaki Osamu
Takafuji Yutaka
Chow Dennis-Doon
Conlin David G.
Daley, Jr. William J.
Edwards & Angell LLP
Sharp Kabushiki Kaisha
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