Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-07-18
2004-02-24
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185150, C365S189110
Reexamination Certificate
active
06697280
ABSTRACT:
Japanese Patent Application No. 2001-221790, filed on Jul. 23, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor capacitance device, a booster circuit and a nonvolatile semiconductor storage device.
Known as a nonvolatile semiconductor device is the MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type wherein the gate insulating layer between a channel and a gate is formed of a laminate consisting of a silicon oxide film, silicon nitride film and silicon oxide film, and where in electric charges are trapped in the silicon nitride film.
The MONOS type nonvolatile semiconductor storage device is disclosed in a literature (Y. Hayashi, et al., in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122 to 123). This literature teaches a MONOS flash memory cell including two nonvolatile memory elements (also termed “MONOS memory elements or cells”) which are controlled by one word gate and two control gates. That is, one flash memory cell has two charge-trapping sites.
In operating the MONOS memory elements, voltages higher than a supply voltage are sometimes applied to the control gates, a bit line and a word line. The voltages higher than the supply voltage are generated by a booster circuit which includes a capacitance element. On the other hand, the MONOS memory element consumes a large current, thereby the size of the capacitance element in the booster circuit needs to be enlarged. However, in a case where the capacitance element is constructed of a MOS capacitor, the distance between the source and drain regions is increased by enlarging the size of the capacitance element. In a region spaced from the source and drain regions, therefore, an inversion layer becomes difficult to be formed on account of increase in a substrate resistance.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a semiconductor capacitance device in which an inversion layer is easily formed.
The present invention may also provide a booster circuit which employs the semiconductor capacitance device of the present invention as a boosting capacitor.
Furthermore, the present invention may provide a nonvolatile semiconductor storage device which generates the drive voltage of a nonvolatile storage element by the booster circuit of the present invention.
According to the first aspect of the present invention, a semiconductor capacitance device comprises:
a P-type semiconductor layer;
an N-type well region which is provided in the P-type semiconductor layer;
a P-type well region which is provided in the N-type well region;
an electrode layer which is provided over the P-type well region with an insulating layer interposed therebetween;
a first N-type impurity layer which is provided in the P-type well region on one side of the electrode layer; and
a second N-type impurity layer which is provided in the P-type well region on the other side of the electrode layer,
wherein the electrode layer has at least one through hole; and
wherein a third N-type impurity layer is provided in the P-type well region at a position facing the through hole.
In the first aspect of the present invention, the third N-type impurity layer is formed in that part of the P-type well region at a position facing the through hole provided in the electrode layer. Accordingly, the third N-type impurity layer is provided between the first N-type impurity layer and the second N-type impurity layer, and thus the resistance between the source and drain regions can be reduced. As a result, the inversion layer of the MOS capacitor is easily formed even in a region which is spaced from the first and second N-type impurity layers.
Besides, in the first aspect of the present invention, a triple well structure is adopted which is formed of the P-type semiconductor layer, the N-type well region and the P-type well region. Therefore, voltage characteristics of the MOS capacitor can be enhanced on the low voltage side thereof.
In this aspect of the present invention, a P-type well contact region may be provided in the P-type well region at a position facing the through hole; and
the third N-type impurity layer may be provided so as to surround the P-type well contact region.
Since the P-type well contact region is provided in the P-type well region at a position facing the through hole, the parasitic resistance of the P-type well region can be reduced. As a result, voltage characteristics of the MOS capacitor can be further enhanced.
According to the second aspect of the present invention, a semiconductor capacitance device comprises:
a P-type semiconductor layer;
an N-type well region which is provided in the P-type semiconductor layer;
an electrode layer which is provided over the N-type well region with an insulating layer interposed therebetween;
a first P-type impurity layer which is provided in the N-type well region on one side of the electrode layer; and
a second P-type impurity layer which is provided in the N-type well region on the other side of the electrode layer,
wherein the electrode layer has at least one through hole; and
wherein a third P-type impurity layer is provided in the N-type well region at a position facing the through hole.
In this aspect of the present invention, the third P-type impurity layer is formed in the N-type well region at a position facing the through hole provided in the electrode layer. Accordingly, the third P-type impurity layer is provided between the first P-type impurity layer and the second P-type impurity layer, and thus the resistance between the source and drain regions can be reduced. As a result, the inversion layer of the MOS capacitor is easily formed even in a region which is spaced from the first and second P-type impurity layers.
In this aspect of the present invention, an N-type well contact region may be provided in the N-type well region at a position facing the through hole; and
the third P-type impurity layer may be provided so as to surround the N-type well contact region.
Since the N-type well contact region is provided in that part of the N-type well region at a position facing the through hole, the parasitic resistance of the N-type well region can be reduced. As a result, voltage characteristics of the MOS capacitor can be further enhanced.
In the semiconductor capacitance device according to the first and second aspects of the present invention, the electrode layer may have a plurality of the through holes which are arranged in first and second directions intersecting each other.
According to the third aspect of the present invention, a booster circuit comprises the semiconductor capacitance device as defined in the first or second aspect of the present invention, as a boosting capacitor.
According to the fourth aspect of the present invention, a nonvolatile semiconductor storage device comprises:
the booster circuit as defined in the third aspect of the present invention;
a memory cell array including a plurality of nonvolatile semiconductor storage elements; and
a drive circuit which drives the nonvolatile semiconductor storage elements on the basis of an output of the booster circuit.
Here, each of the nonvolatile semiconductor storage elements may include one word gate, and first and second nonvolatile memory elements which are controlled by first and second control gates.
Besides, each of the first and second nonvolatile memory elements may include an ONO film formed of an oxide film (O), a nitride film (N) and an oxide film (O), as a trap site for electric charges, and data may be programmed in the trap site.
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Elms Richard
Nguyen Tuan T.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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