Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2001-11-26
2004-08-31
Wong, Edna (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S222000
Reexamination Certificate
active
06783652
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing a wiring board and, more particularly, to a process for manufacturing a circuit board in which a first wiring pattern formed on a first surface of a substrate made of resin as a basic material is electrically connected to a second wiring pattern formed on a second surface opposite to the first surface by means of vias penetrating through the substrate.
2. Description of the Related Art
One of the known processes for manufacturing a wiring board on which semiconductor elements, or other electronic elements, is mounted are called a “damascene” method.
An example of such “damascene” method is shown in FIGS.
10
(
a
) to
10
(
e
). FIG.
10
(
a
) is a cross-sectional view of a wiring board
100
on which wiring patterns
140
a
are formed. The wiring board
100
is made of resin as a basic material. The wiring pattern
140
a
can be formed by coating photo-resist on the respective surfaces of the resin plate on which copper foils are attached beforehand, light-exposing thereto in accordance with a predetermined pattern for forming the wiring patterns
140
a
, developing the same to form a resist pattern, and etching the exposed portions of the copper foil using a masking of the resist pattern to remove the exposed area.
The wiring patterns
100
a
formed on the respective surfaces of the wiring board
100
are electrically connected to each other by means of through holes
120
. The through holes
120
are formed by forming via holes by drilling the wiring board
100
, and then forming a thin metal film on the inner wall of the via holes by electroless-plating, and then forming a conductor layer on the inner wall of the via holes by electroplating using the thin metal film as a power-supply layer.
In addition, on the respective surfaces
160
a
and
160
b
of the wiring board
100
shown in FIG.
10
(
a
) resin layers
160
a
and
160
b
are formed by coating the same with a resin, such as a polyimide or an epoxy resin, as shown in FIG.
10
(
b
).
As shown in FIG.
10
(
c
), via recesses
130
and wiring pattern recesses
132
are formed on the resin layers
160
a
and
160
b
by irradiating laser light, such as, CO
2
laser or excimer laser light.
The wiring board
100
thus having the resin layers
160
a
and
160
b
formed with the via recesses
130
and wiring pattern recesses
132
is now processed as follows. As shown in FIG.
10
(
d
), after a metal thin film is formed on the inner wall of the via recesses
130
and wiring pattern recesses
132
and on the surface of the resin layer
160
a
by electroless-plating of copper or the other, an electro-plating is applied to fill the via recesses
130
and wiring pattern recesses
132
with plated metal
134
using the metal thin film as a power-supply layer. In this case, the surface of the resin layer
160
a
is also coated with a plated metal
134
.
Therefore, the plated metal
134
covering the surface of the resin layer
160
a
is removed by polishing, as shown in FIG.
10
(
e
), and thus the surface of the resin layer
160
a
is exposed. By such a polishing the wiring patterns
150
a
consisting of vias
120
formed with the filled plated metal
134
in the via recesses
130
and plated metal
134
filled in the wiring pattern
132
recesses are exposed on the same surface as the surface of the resin layer
160
a
, so that the wiring patterns
150
a
are formed on the surface of the resin layer
160
a.
According to the “damascene” method as mentioned above, very fine and dense wiring patterns can be obtained as compared with a conventional wiring board which is made by a “sub-tractive” method or a “semi-additive” method as known in the prior art.
However, the wiring patterns formed on the respective surfaces of the wiring board
100
are electrically connected with each other by means of through holes
120
. Since the wiring pattern and through holes
120
are formed respectively by the separate processes, it is difficult to reduce the production cost of the wiring board
100
.
Also, since the via recesses
130
and wiring pattern recesses
132
of the resin layers
160
a
and
160
are formed by irradiating laser light, such as CO
2
laser or excimer laser light, a facility for irradiating laser light is necessary. Also, since the depth of the via recesses
130
is different from that of the wiring pattern recesses
132
, it is necessary to precisely control the intense or irradiation time of laser beam. Thus, the production cost of the obtained wiring board is high.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process for manufacturing a wiring board capable of easily forming via recesses for filling with plating metal and of reducing the production cost of the wiring board.
According to the present invention, there is provided a process for manufacturing a wiring board, said process comprising the following steps of: making a resin plate having wiring pattern recesses and via through holes; coating all of the surfaces of the resin plate including inner walls of said wiring pattern recesses and via through holes with a metal film; applying an electro-plating using said metal film as a power-supply layer to fill a plated metal into said wiring pattern recesses and via through holes; and removing said metal film formed on said resin plate except for the inner walls of said wiring pattern recesses and via through holes, so that wiring pattern and vias are exposed on a surface the same as that of said resin plate.
The resin plate is formed by a press-forming process. Otherwise, the resin plate can be formed by an injection molding process.
The above mentioned process further comprises the following steps of: forming pads on one of surfaces of the wiring board to which external connecting terminals are to be attached.
The above mentioned process further comprises the following steps of: using said wiring board as a core substrate; and forming wiring patterns on the respective surface of the core substrate by means of resin layers to obtain a multi-layer wiring board.
According to another aspect of the present invention, there is provided a process for manufacturing a multi-layer wiring board, said process comprising:
(a) manufacturing a core substrate comprising the steps of: making a resin plate having wiring pattern recesses and via through holes; coating all of the surfaces of the resin plate including inner walls of said wiring pattern recesses and via through holes with a metal film; applying an electro-plating using said metal film as a power supply layer to fill a plated metal into said wiring pattern recesses and via through holes; and removing said metal film formed on said resin plate except for the inner walls of said wiring pattern recesses and via through holes, so that wiring pattern and vias are exposed on a surface same as that of said resin plate; and
(b) forming resin layers on respective surfaces of said core substrate so that said resin layers includes wiring pattern recesses and via through holes;
(c) coating all of surfaces of said resin layers including inner walls of said wiring pattern recesses and via through holes with a metal film;
(d) applying an electro-plating using said metal film as a power supply layer to fill a plated metal into said wiring pattern recesses and via through holes; and
(e) removing said metal film attached to said resin layer except for the inner walls of said wiring pattern recesses and via through holes, so that wiring pattern and vias are exposed on a surface same as that of said resin plate.
REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 5093279 (1992-03-01), Andreshak et al.
patent: 5333379 (1994-08-01), Odaira et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 6254758 (2001-07-01), Koyama
patent: 6355153 (2002-03-01), Uzoh et al.
Horikawa Yasuyoshi
Iijima Takahiro
Rokugawa Akio
Paul & Paul
Shinko Electric Industries Co. Ltd.
Wong Edna
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