Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-10-12
2004-08-17
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
With measuring or testing
C438S017000, C438S114000, C438S465000
Reexamination Certificate
active
06777250
ABSTRACT:
DETAILED DESCRIPTION OF THE INVENTION
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing wafer level semiconductor device and a semiconductor device wherein a plurality of chips and chip size packages (hereinafter referred to as CSP) are formed on the wafer and substrate.
There has been proposed a semiconductor package having the structure that an external output terminal formed of a projected electrode is provided on a chip, in order to provide the shape of semiconductor package sealed with resin closely to a semiconductor element (hereinafter referred to as chip) as much as possible, at least the side surface of projected electrode is sealed with resin under the wafer condition and thereafter each chip is diced. (Japanese Published Unexamined Patent Application No. HEI 10-79362; U.S. patent application Ser. No. 09/029,608)
The present invention relates to a method for providing manufacturing history used to conduct failure search of such wafer level semiconductor device and a semiconductor device manufactured using such method.
Information including manufacturer name, type, manufacturing lot or the like has been marked on the resin of a semiconductor device surface in the semiconductor device of the type other than the wafer level semiconductor device, namely the semiconductor package after the dicing and resin sealing. If a failure has occurred, history of manufacturing lot can be searched from this marking information and thereby cause of fault can be identified effectively.
The similar information is also marked in the wafer level semiconductor device of the related art.
In manufacture of semiconductor device using wafer including wafer level semiconductor device, manufacturing processes are all performed under the wafer condition but a fault is sometimes generated from the particular position on the wafer. In this case, it is required to detect where a fault is generated on the wafer but since no marking is conducted on the chip in the manufacturing method of the related art, it is impossible to identify where a fault has occurred on the wafer.
Even if marking is conducted on the chip, it is required to execute the process to melt the resin and it is considerably complicated to confirm the marking after the sealing with resin.
BRIEF SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method of manufacturing semiconductor device in the method of manufacturing wafer level semiconductor device where a fault can be searched from the marked information even after the sealing resin is formed on the wafer and a semiconductor device manufacturing with such semiconductor device manufacturing method.
The object of the invention is achieved by a method of manufacturing wafer level semiconductor device, comprising sealing process for sealing, with resin material, the front surface of a wafer having the front and rear surfaces and having formed a plurality of semiconductor chips on the front surface, first marking process for marking the position information corresponding to each chip in the region of each chip at the rear surface of the wafer, process for conducting electrical test to each chip, second marking process for marking the result of the electrical test corresponding to each chip in the region of each chip at the rear surface of the wafer, and dicing process for dicing each chip.
Further, the object of the invention is achieved by a method of manufacturing wafer level semiconductor device comprising sealing process for sealing, with resin material, the front surface of a wafer having the front and rear surfaces and having formed a plurality of semiconductor chips on the front surface thereof, process for conducting electrical test to each chip, marking process for marking, in the region of each chip at the rear surface of the wafer, the position information corresponding to each chip and the result of the electrical test, and dicing process for dicing each chip.
Further, the object of the invention is achieved by a method of manufacturing wafer level semiconductor device comprising sealing process for sealing, with resin material, the front surface of a wafer having the front and rear surfaces and having formed a plurality of semiconductor chips on the front surface, attaching process for attaching, to the rear surface of wafer, a resin sheet on which marking is made on the wafer to indicate position of each chip and dicing process for dicing each chip.
Further, the object of the invention is achieved by a semiconductor device comprising a semiconductor chip diced from the predetermined position of wafer wherein circuits are formed at the front surface, a resin sealing the front surface of the semiconductor chip, an external output terminal exposed from the resin and connected with the circuits, and a marking provided at the rear surface of the semiconductor chip to indicate the predetermined position of the wafer.
Further, the object of the invention is achieved by a semiconductor device comprising a semiconductor chip diced from the predetermined position of a wafer where circuits are formed at the front surface, a resin for sealing the front surface of the semiconductor chip, an external output terminal exposed from the resin and connected to the circuit, resin sheet attached to the rear surface of the semiconductor chip and a marking for indicating the predetermined position of the wafer printed on the resin sheet.
Each means described above includes following operations.
According to the first manufacturing method described above, resin sealing and electrical test are performed under the wafer condition without dicing individual chips from the wafer and therefore wafer manufacturing record can easily be corresponding to the chip manufacturing record. Moreover, marking can be made in the wafer condition before individual chips are diced into each chip. Therefore, when the manufacturing information is described at the time of marking, the chip manufacturing record is also left together with the position information on the wafer of chip to individual chip after the dicing in such a case that the manufacturing information is described at the time of marking. Thereby, if a defective product is generated, the cause may be searched easily and trace-ability can be improved.
According to the second manufacturing method described above, since the marking of position information can be executed in the same process as the marking of the result of electrical test, effective marking may be realized by attempting twice the marking process as described in the first method.
According to the third manufacturing method described above, since the resin sheet is used, the semiconductor package on which at least position information is marked can be structured only by attaching the resin sheet and the making can be done within a short period of time.
According to the first semiconductor device as described above, the information suggesting where the chip in the semiconductor package is located during the manufacturing process is marked and the manufacturing location record is left and therefore if a fault is generated, the cause of such fault may be searched easily and thereby trace-ability can be improved.
According to the second semiconductor device as described above, since the resin sheet is used in addition to the operation effect similar to that of the first device, the semiconductor package on which the position information is marked can be obtained at a low price.
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Nakajyo Shinsuke
Sakoda Hideharu
Yoneda Yoshiyuki
Armstrong Kratz Quintos Hanson & Brooks, LLP
Elms Richard
Fujitsu Limited
Wilson Christian D.
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