1996-07-30
1998-01-13
Sheikh, Ayaz R.
G06F 900
Patent
active
057088039
ABSTRACT:
A data processor, with high processing performance in many fields of application, having a selector 41 which enables a cache memory of direct map system to be selectively used as a built-in cache memory or a built-in RAM in order to realize a data processor which can perform high-speed processing by decreasing the number of abortions of the processing as much as possible when branch is predicted in the pipeline processing mechanism, and an FB register 61B which holds an address to be accessed so that cache memory or external storage (main storage 28) may be accessed when branch is not predicted in the pipeline processing mechanism and only a cache memory may be accessed but accessing to the main storage 28 may be prohibited when branch is predicted, wherein the main storage 28 can be accessed by the address held in the FB register 61B at the moment it becomes accessible.
REFERENCES:
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4764861 (1988-08-01), Shibiya
patent: 4881170 (1989-11-01), Morisada
patent: 4984154 (1991-01-01), Hanatani et al.
patent: 5442756 (1995-08-01), Grochoski et al.
patent: 5479622 (1995-12-01), Grohoski et al.
patent: 5509137 (1996-04-01), Itonitsu et al.
patent: 5511175 (1996-04-01), Favor et al.
80960CA User's Manual, Mitsubishi Electric Corporation, Mar. 1989, B47-B49 "Computer Architecture A Quantitative Approach", Patterson, David S. et al., pp. 272-277k.
Ishimi Kouichi
Saito Yuichi
Mitsubishi Denki & Kabushiki Kaisha
Sheikh Ayaz R.
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