Telecommunications – Transmitter – Noise or interference elimination
Reexamination Certificate
2002-10-25
2004-06-29
Appiah, Charles (Department: 2686)
Telecommunications
Transmitter
Noise or interference elimination
C455S126000, C330S149000, C330S151000, C375S296000
Reexamination Certificate
active
06757525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a distortion compensating apparatus, and in particular to an apparatus for compensating a distortion generated upon amplifying a linear modulation signal at a power amplifier, a low noise amplifier, or the like used for a wireless communication system or the like.
A power amplifier or the like, which amplifies a linear modulated signal, when an input power exceeds a fixed value as shown by power input/output characteristics of
FIG. 19A
, exhibits a nonlinear distortion range as shown by a characteristic A. A frequency spectrum of this distortion range in the vicinity of a transmission frequency f
0
in the power amplifier causes side lobes to rise as shown by a characteristic D of
FIG. 19B
, and leak to an adjacent channel, resulting in an adjacent interference.
Accordingly, in order to obtain a linear characteristic B shown in
FIG. 19A
, it is necessary to preliminarily provide a characteristic C and to obtain a characteristic E after the compensation of a distortion as shown in FIG.
19
B.
2. Description of the Related Art
Thus, as an example of a distortion compensating method for obtaining a desired linear signal in which a distortion is removed from the output of an amplifier by preliminarily adding a characteristic opposite to a distortion characteristic of the amplifier to an input signal of the amplifier, an adaptive predistorter (predistortion) type compensating apparatus as shown in
FIG. 20
is generally known.
In
FIG. 20
, a power amplifier
1
amplifies a transmission signal (hereinafter, occasionally referred to as a reference signal) S
T
to provide an output signal S
O
, which is sent to a subtractor
2
as a feedback signal S
F
together with the transmission signal S
T
. The difference between both signals inputted at the subtractor
2
is sent to an adaptive distortion compensating coefficient (DCC) generator
3
.
Then, the adaptive distortion compensating coefficient generator
3
generates a distortion compensating coefficient “h” based on the output of the subtractor
2
as well as the power or the amplitude of the then transmission signal S
T
, and multiplies the transmission signal S
T
by the distortion compensating coefficient h at a multiplier
4
, thereby generating a predistorter signal. By inputting this predistorter signal to the power amplifier
1
, the output distortion of the power amplifier
1
is compensated.
FIG. 21
shows details of the adaptive predistorter type distortion compensating apparatus as a prior art example (1) (basic arrangement).
In this prior art example (1), the adaptive distortion compensating coefficient generator
3
in the distortion compensating apparatus conceptually shown in
FIG. 20
is composed of an inverter
14
for generating a conjugate complex number, multipliers
15
-
17
, an adder
18
, an address generator
19
, and a distortion compensating table
20
. It is to be noted that multipliers
4
,
15
, and
16
are complex multipliers.
Also, a modulator MOD, which is not shown in
FIG. 20
, is connected between the power amplifier
1
and the multiplier
4
. The modulator MOD is composed of an LPF (low-pass filter)
5
, a D/A (digital/analog) converter
6
, a local oscillator
7
, and a multiplier
8
, where a baseband predistorter signal from the multiplier
4
through the LPF
5
is converted into an IF (intermediate frequency) signal.
Also, a digital orthogonal demodulator DEM is provided between the power amplifier
1
and the subtractor
2
. This demodulator DEM is composed of an A/D converter
9
, a local oscillator
11
, a complex multiplier
12
, and an LPF
13
, where an IF feedback signal S
F
is converted into a baseband signal S
FB
to be provided to the subtractor
2
.
FIG. 22
shows an arrangement of the digital orthogonal demodulator DEM shown in FIG.
21
. The multiplier
12
is composed of complex multipliers
121
and
122
, respectively converting an IF feedback signal {circle around (
1
)} from the A/D converter
9
into signals {circle around (
2
)} with cos &ohgr;t and sin &ohgr;t signals from the local oscillator
11
.
Since the signals {circle around (
2
)} include a high frequency component, signals {circle around (
3
)} only of the baseband are outputted respectively from LPF's
131
and
132
, so that Ich and Qch components of the feedback signal S
FB
are respectively provided to the subtractor
2
.
A distortion amount to be compensated in
FIG. 21
is estimated by calculations of the following equations.
h
n
(
p
)=
h
n−1
(
p
)+&mgr;
e
(
t
)
u
*(
t
) Eq.(1)
e
(
t
)=
x
(
t
)−
y
(
t
) Eq.(2)
u
(
t
)=
x
(
t
)
f
(
p
)≅
h
*
n−1
(
p
)
y
1
(
t
) Eq.(3)
h
n−1
(
p
)h*
n−1
(
p
)≅1 Eq.(4)
y
(
t
)=
h
n−1
(
p
)
x
(
t
)
f
(
p
) Eq.(5)
p=|x
2
(
t
)| Eq.(6)
In the above equations, x(t) is an input baseband signal, f(p) is a distortion function of the power amplifier
1
itself, h
n
(p) is a distortion compensating coefficient to be updated, and &mgr; is a step size parameter. Furthermore, in the above equations, x, y, f, h, u, and e are complex numbers, and * indicates a conjugate complex number. Also, u(t) is approximated as given in Eq.(4) on the assumption that the amplitude distortion of the power amplifier
1
is not very large.
The meanings of the above equations in the above-mentioned condition will now be described.
In Eq.(1), h
n
(p) is an estimated distortion compensating coefficient to be updated, and is inputted to the table
20
which stores the distortion compensating coefficients. From an output y(t) of the power amplifier
1
, y*(t) is obtained by the inverter
14
which is a conjugate complex number generation circuit. Accordingly, supposing that the estimated distortion compensating coefficient at the last sampling is h
n−1
(p), the output of the multiplier
15
assumes y*(t)h
n−1
(p).
The output of the multiplier
15
is further multiplied by an output e(t) of the subtractor
2
at the multiplier
16
to assume y*(t) h
n−1
(p)e(t). Furthermore, it is multiplied by a step size parameter &mgr; at the multiplier
17
.
Accordingly, the estimated distortion compensating coefficient to be updated assumes h
n
(p)=&mgr;y*(t)h
n−1
(p)e(t)+h
n−1
(p).
Supposing that y*(t)h
n−1
(p)=u*(t), the distortion compensating coefficient h
n
(p) can be expressed as the above-mentioned Eq.(1).
Also, e(t) is the output of the subtractor
2
as expressed by Eq.(2), and is an error between the input x(t) and the output y(t). Furthermore, u(t) in Eq.(3) is approximated as expressed by Eq.(4) on the assumption that the amplitude distortion of the power amplifier
1
is not very large. Accordingly, the conjugate complex number u(t) of u*(t) is expressed as Eq.(3).
Eq.(6) means that the address generator
19
is a circuit for determining the power of the input signal x(t). When it is supposed to be a circuit for determining the amplitude of the input, Eq.(6) is expressed by |x(t)|. Alternatively, when it is supposed to be a function of the power or the amplitude, Eq.(6) is expressed by g(|x(t)|
2
) and g(|x(t)|), respectively.
Furthermore, the value determined by the address generator
19
assumes a write/read address for the table
20
storing the distortion compensating coefficient h
n
(p).
In case where a write update and a multiplication of the estimated distortion compensating coefficient h
n
(p) with the input signal x(t) are independently performed, predistortion is always enabled without an influence of a delay on the system.
Thus, in the above-mentioned prior art example (1), the distortion compensating coefficient h
n
(p) is generated referring to the distortion compensating table, and is multiplied by the transmission signal S
T
, thereby preliminarily generating the predistorter signal. Thus, the characteristic of the power amplifier
1
Fudaba Nobukazu
Hamada Hajime
Hamano Mitsuharu
Hanada Koichi
Ishikawa Hiroyoshi
Appiah Charles
Katten Muchin Zavis & Rosenman
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