Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2003-01-21
2004-12-28
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S685000, C257S686000, C257S690000, C257S692000, C257S693000
Reexamination Certificate
active
06836010
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device mounted by wire bonding and to a method of producing the semiconductor device.
2. Description of the Related Art
Conventionally, semiconductor devices of a package configuration, such as the Small Outline Package (SOP), the Dual Inline Package (DIP), the Pin Grid Array (PGA), and the Quad Flat Package (QFP), which all accommodate a semiconductor chip in a package, have been known. Moreover, various semiconductor devices of a multi-chip package configuration, in which several semiconductor chips are accommodated in a single package, have been proposed in order to improve packaging density.
Examples of documents concerning semiconductor devices of the multi-chip package configuration include the following.
Document 1: Japanese Patent Application Laid-open Publication (JP-A) No. 2000-332194
Document 2: Japanese Patent Application Laid-open Publication (JP-A) No. 2001-7277
FIGS. 14A and 14B
are schematic structural views of a conventional SOP semiconductor device, with
FIG. 14A
being a plan view and
FIG. 14B
being a longitudinal sectional view.
FIGS. 15A and 15B
are schematic structural views of another conventional SOP semiconductor device in which exterior pull-out lead positions are different from those of
FIGS. 14A and 14B
, with
FIG. 15A
being a plan view and
FIG. 15B
being a longitudinal sectional view.
In the semiconductor device of
FIGS. 14A and 14B
, a semiconductor chip
20
A is mounted using a lead frame
10
A. As shown in
FIG. 14A
, the lead frame
10
A includes a die pad
11
A for mounting a semiconductor chip, with the die pad
11
A being substantially rectangular in plan view. A plurality of leads
12
A are vertically disposed a predetermined distance away from upper and lower edges of the die pad
11
A. Each lead
12
A includes an inner lead portion disposed with a bonding pad
13
A and an outer lead portion that is pulled out to the exterior.
The semiconductor chip
20
A, which is rectangular when seen in plan view, is fixed on the die pad
11
A. As seen in
FIG. 14A
, bonding pads
21
A are disposed near upper and lower edges of an upper surface of the semiconductor chip
20
A in correspondence to the positions at which the bonding pads
13
A of the lead frame
10
A are disposed. The bonding pads
21
A of the semiconductor chip
20
A are connected to the bonding pads
13
A of the lead frame
10
A by wires
14
A. The semiconductor chip
20
A and the wires
14
A are resin-sealed with a resin member
15
A.
Because the semiconductor device of
FIGS. 15A and 15B
is packaged using a lead frame
10
B, in which the pull-out direction of the leads is different from that of the lead frame
10
A of
FIGS. 14A and 14B
, a semiconductor chip
20
B is used in which the positions at which the bonding pads are disposed are different from those of the semiconductor chip
20
A of
FIGS. 14A and 14B
.
Namely, in the lead frame
10
B of
FIGS. 15A and 15B
, plural leads
12
B are, as shown in
FIG. 15A
, horizontally disposed at a predetermined distance away from left and right edges of a die pad
11
B, which is rectangular in plan view. Each lead
12
B includes an inner lead portion disposed with a bonding pad
13
B and an outer lead portion that is horizontally drawn out.
Although the semiconductor chip
20
B, which is rectangular in plan view and fixed on the die pad
11
B, has a function that is identical to that of the semiconductor chip
20
A of
FIGS. 14A and 14B
, it is newly created distinct from the semiconductor chip
20
A of
FIGS. 14A and 14B
so that the bonding pads
21
B are disposed near left and right edges of the upper surface in order to correspond to the positions at which the bonding pads
13
B of the lead frame
10
B are disposed. After the bonding pads
21
B of the semiconductor chip
20
B have been connected to the bonding pads
13
B of the lead frame
10
B by wires
14
B, the semiconductor chip
20
B and the wires
14
B are resin-sealed with a resin member
15
B.
FIGS. 16A
,
16
B and
16
C are schematic structural views showing a semiconductor device of a conventional multi-chip package configuration, with
FIG. 16A
being a plan view seen from an upper surface,
FIG. 16B
being a bottom view seen from an undersurface, and
FIG. 16C
being a longitudinal sectional view. Elements in common with elements of
FIGS. 15A and 15B
are designated by common reference numerals.
In this semiconductor device, semiconductor chips
20
B and
20
C that have the same function are mounted on an upper surface and on an undersurface of the die pad
11
B of the lead frame
10
B of
FIGS. 15A and 15B
for the purpose of, for example, doubling memory capacity.
As shown in
FIG. 16A
, the lead frame
10
B includes the die pad
11
B, which is rectangular in plan view, and plural leads
12
B that are horizontally disposed at a predetermined distance away from left and right edges of the die pad
11
B. The leads
12
B include inner lead portions disposed with bonding pads
13
B (left-side bonding pads
13
B-
11
,
13
B-
12
, . . . , and right-side bonding pads
13
B-
21
,
13
B-
22
, . . . ) and outer lead portions that are horizontally pulled out.
Bonding pads
21
B (left-side bonding pads
21
B-
11
,
21
B-
12
, . . . , and right-side bonding pads
21
B-
21
,
21
B-
22
, . . . ) are disposed near left and right edges of an upper surface of the semiconductor chip
20
B on the upper side of the die pad
11
B in correspondence to the bonding pads
13
B-
11
,
13
B-
12
, . . . ,
13
B-
21
,
13
B-
22
, . . . of the lead frame
10
B. The left-side bonding pads
21
B-
11
,
21
B-
12
, . . . are connected to the left-side bonding pads
13
B-
11
,
13
B-
12
, . . . of the lead frame
10
B via plural wires
14
B. The right-side bonding pads
21
B-
21
,
21
B-
22
, . . . are connected to the right-side bonding pads
13
B-
21
,
13
B-
22
, . . . of the lead frame
10
B.
When a semiconductor chip having the same structure (i.e., when the disposition of the bonding pads thereof is the same) as that of the semiconductor chip
20
B on the upper surface of the die pad
11
B is used as the semiconductor chip
20
C on the undersurface of the die pad
11
B, wires
14
C cross and short because the disposition of the bonding pads is reversed right/left or up/down when seen from the upper side of the die pad
11
B. In order to prevent this, a mirror chip, in which the disposition of the bonding pads and inner element circuitry are inverted (i.e., so that top and bottom face, or mirror, each other) to become rotationally symmetrical with respect to the semiconductor chip
20
B on the upper surface of the lead frame
10
B, is used for the semiconductor chip
20
C on the undersurface of the lead frame
10
B.
As shown in
FIG. 16B
, the mirror chip-structure semiconductor chip
20
C is disposed with bonding pads
21
C (right-side bonding pads
21
C-
11
,
21
C-
12
, . . . , and left-side bonding pads
21
C-
21
,
21
C-
22
, . . . ) near right and left edges thereof (since the semiconductor chip
20
C is being viewed from its undersurface, left/right are opposite) in correspondence to the bonding pads
13
B-
11
,
13
B-
12
, . . . ,
13
B-
21
,
13
B-
22
, . . . of the lead frame
10
B. The right-side bonding pads
21
C-
11
,
21
C-
12
, . . . are connected to the left-side (when seen from the upper surface of the lead frame
10
B) bonding pads
13
B-
11
,
13
B-
12
, . . . by the plural wires
14
C. The left-side bonding pads
21
C-
21
,
21
C-
22
, . . . are connected to the right-side (when seen from the upper surface of the lead frame
10
B) bonding pads
13
B-
21
,
13
B-
22
, . . .
The semiconductor chips
20
B and
20
C and the wires
14
B and
14
C are resin-sealed with the resin member
15
B.
However, there have been the following problems (1) and (2) in the aforementioned conventional semiconductor devices and their methods of production.
(1) Problems in the Conventional Devices of
FIGS. 14A
to
15
B
When the semiconductor chip
20
A of
FIGS. 14A and 14B
is mounted in
Oki Electric Industry Co. Ltd.
Soward Ida M.
Volentine Francos & Whitt PLLC
Zarabian Amir
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