Coded data generation or conversion – Converter compensation
Reexamination Certificate
2003-09-10
2004-11-30
Young, Brian (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S155000
Reexamination Certificate
active
06825783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to analog-to-digital (“A/D”) converters, and more particularly to a multiple stage A/D converter with a pipeline structure.
2. Description of Related Art
Generally, in designing an A/D converter with a pipeline structure, a one-bit overlap coding technique is used that overlaps one bit of digital data in each stage to a bit of digital data in corresponding next stages for correcting an offset error caused in the stage. For example, a three-stage A/D converter for producing 10-bit data is designed to have 4-bit data in each stage from a first to third stages, and 1 bit of data in the respective second and third stages is used for error correction, so that an error caused in a previous stage is corrected in a subsequent stage.
However, an A/D converter with an error correction function described above takes up two times the area and consumes two times the power in comparison with an A/D converter without an error correction bit for each stage. However, since an A/D converter without an offset error correction function does not operate correctly, an error correction bit must be used in an A/D converter with a pipeline structure.
As shown in
FIG. 1
, a conventional coding method for implementing an A/D converter is indicated generally by the reference numeral
100
. The coding method
100
is of a 4 stage A/D converter for processing 14-bit data. A first stage has 5 bits of data, while a second, third, fourth and fifth stage each has 4 bits of data, respectively. In the second and third stages, one bit of data is used as an error correction bit for correcting an error caused in a corresponding previous stage.
In the method
100
, a normal range does not have an offset error therein. Thus, the result of a previous stage, such as a first stage that falls in the normal range, is used in a next stage, such as a second stage. An ADD
1
and a SUB
1
are signals for adding or subtracting one bit to or from a result of a previous stage, respectively, when there is an offset error detected in data of the previous stage.
The conventional multi-stage A/D converter as described above is disadvantageous in that its circuitry is complicated, takes up a large area on a chip, and consumes a high amount of power because every stage from a second stage to the last stage has an error correction bit.
SUMMARY OF THE INVENTION
It is a feature of embodiments of the present invention to provide a multi-stage A/D converter with a pipeline structure, which has an error correction bit in the data of only a second stage.
It is another feature of embodiments of the present invention to provide a multiple stage A/D converter with a pipeline structure capable of being implemented in a small chip and consuming a small amount of power.
It is a further feature of embodiments of the present invention to provide a coding method of a multi-stage A/D converter with a pipeline structure.
In accordance with one aspect of the present invention, there is provided a multi-stage A/D converter with a pipeline structure comprising (a) a sample-and-hold unit for receiving, sampling and holding analog input signals, (b) a converter section being comprised of a plurality of stages for receiving an output of the sample-and-hold unit and generating digital data with a predetermined number of bits, and (c) a correction circuit for correcting an offset error by overlapping a least significant bit (“LSB”) of data of a previous stage and a most significant bit (“MSB”) of data of a subsequent stage when an offset error is caused in the previous stage, receiving the digital data from each stage of the converter section, and outputting digital output data, wherein a second stage of the converter section has an error correction bit in the digital data thereof for correcting an error caused in a first stage but a third and other stages coming after the third stage do not have an error correction bit.
Preferably, each stage of the converter section may comprise a flash converter for receiving the output of the sample-and-hold unit and generating digital signals corresponding to the received analog signals, and a multiplying digital-to-analog converter (“MDAC”) for receiving the digital signals from the flash converter, converting the received digital signals to analog signals, acquiring a difference between the output of the sample-and-hold unit and the converted analog signals, making a residue signal using the difference, and amplifying the residue signal.
Preferably, the converter section may comprise a first stage having the flash converter with 5 bits and the MDAC with 5 bits, a second stage having the flash converter with 4 bits and the MDAC with 4 bits, a third stage having the flash converter with 3 bits and the MDAC with 3 bits, and a fourth stage having the flash converter with 3 bits, and wherein the second stage has the error correction bit for correcting the error caused in the first stage and a total of 14 bits of digital output data are generated from the A/D converter.
Preferably, gains for the MDACs of the first and the second stages may be 16, respectively, and a gain of the MDAC of the third stage may be 8.
In accordance with another aspect of the present invention, there is provided a coding method for designing a multi-stage A/D converter with pipeline structure comprising (a) a sample-and-hold unit for receiving, sampling and holding analog input signals, (b) a converter section being comprised of a plurality of stages for receiving an output of the sample-and-hold unit and generating digital data with a predetermined number of bits, and (c) a correction circuit for correcting an offset error by overlapping an LSB of data of a previous stage and an MSB of data of a subsequent stage when an offset error is caused in the previous stage, receiving the digital data from each stage of the converter section, and outputting digital output data, wherein a second stage of the converter section has an error correction bit in the digital data thereof for correcting an error caused in a first stage but a third and other stages coming after the third stage do not have an error correction bit.
REFERENCES:
patent: 5635937 (1997-06-01), Lim et al.
patent: 5977894 (1999-11-01), McCarroll et al.
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