Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-03
2004-08-24
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185230, C365S185240, C365S185280, C365S185290, C365S210130
Reexamination Certificate
active
06781882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and a data erasing method thereof, and more particularly to a flash memory and a data erasing method thereof.
2. Description of the Background Art
A flash memory is a nonvolatile semiconductor storage device capable of electrically writing and erasing data. The flash memory comprises a memory cell array having a plurality of memory cells provided in a matrix, and each memory cell includes a memory cell transistor having a floating gate. A threshold voltage of the memory cell transistor is changed depending on whether an electron is accumulated in the floating gate, and data are stored in a memory cell depending on a difference in the threshold voltage.
At present, the mainstream of the flash memory is an NOR type flash memory. In this specification, description will be given by taking, as an example, a so-called channel whole surface extraction type NOR flash memory in which the electron accumulated in a floating gate is extracted into the whole surface of a channel region in a data erasing operation in the NOR type flash memory.
FIG. 47
is a flow chart for explaining a data erasing operation in a conventional flash memory. When an erasing command is input at a step SP
1
, a batch writing pulse having a predetermined voltage value and a predetermined pulse width is applied to all memory cell transistors at a step SP
2
. At a step SP
3
, next, an erasing pulse having a predetermined voltage value and a predetermined pulse width is applied to all the memory cell transistors.
At a step SP
4
, next, erase verify is carried out to decide whether or not data of all the memory cells are erased. If there is at least one memory cell in which the data are not erased, that is, a result of the decision in the step SP
4
is “FAIL”, the process proceeds to a step SP
5
in which each of the voltage values of the batch writing pulse and the erasing pulse is updated such that a pulse intensity is increased. Then, the batch writing pulse and the erasing pulse which have the voltage values updated are applied again at the steps SP
2
and SP
3
, respectively. The operations of the steps SP
2
to SP
5
are repeated until the data of all the memory cells are erased, that is, the result of the decision in the step SP
4
is obtained as “PASS”.
If the result of the decision in the step SP
4
is “PASS”, the process proceeds to a step SP
6
in which overerase verify is carried out to decide whether or not there is a memory cell transistor set in an overerase state by excessive data erase. If there is no memory cell transistor set in the overerase state, that is, the result of the decision in the step SP
6
is “PASS”, the process proceeds to a step SP
10
and the data erasing operation is thus ended.
If there is at least one memory cell transistor set in the overerase state, that is, a result of the decision in the step SP
6
is “FAIL”, the process proceeds to a step SP
7
in which a rewriting pulse for each bit is applied to the memory cell transistor set in the overerase state. At a step SP
8
, next, the overerase verify is carried out again in order to decide whether or not all the memory cell transistors set in the overerase state are recovered from the overerase state. If at least one memory cell transistor set in the overerase state is still present, that is, a result of the decision in the step SP
8
is “FAIL”, the process returns to the step SP
7
in which the rewriting pulse for each bit is applied again to the memory cell transistor set in the overerase state. The operations of the steps SP
7
and SP
8
are repeated until the presence of the memory cell transistor set in the overerase state is eliminated, that is, the result of the decision in the step SP
8
is obtained as “PASS”.
If the result of the decision in the step SP
8
is “PASS”, the process proceeds to a step SP
9
in which overrewrite verify is carried out to decide whether or not there is a memory cell transistor set in the overrewrite state by excessive data rewrite. If there is no memory cell transistor set in the overrewrite state, that is, a result of the decision in the step SP
9
is “PASS”, the process proceeds to a step SP
10
and the data erasing operation is thus ended.
If there is at least one memory cell transistor set in the overrewrite state, that is, the result of the decision in the step SP
9
is “FAIL”, the process returns to the step SP
2
and the operations at and after the step SP
2
are carried out again.
According to the conventional nonvolatile semiconductor storage device and data erasing method thereof, a batch writing pulse and an erasing pulse which have predetermined voltage values and predetermined pulse widths are applied at the first steps SP
2
and SP
3
to be executed immediately after the step SP
1
irrespective of the number of the data erasing operations, for example, irrespective of a first data erasing operation or a 10000th data erasing operation. More specifically, starting voltage values of the pulse intensities of the batch writing pulse and the erasing pulse are constant irrespective of the number of the data erasing operations.
In the flash memory, an electron is injected into a floating gate to write data to a memory cell and the electron is extracted from the floating gate to erase the data of the memory cell. As the number of the data erasing operations is increased, an electron injection efficiency and an electron extraction efficiency are reduced.
According to the conventional nonvolatile semiconductor storage device and data erasing method thereof, however, the starting voltage values of the pulse intensities of the batch writing pulse and the erasing pulse are constant irrespective of the number of the data erasing operations as described above. In the data erasing operation to be carried out after a large number of data erasing operations have already been executed, therefore, there is a higher possibility that the result of the decision in the step SP
4
might be “FAIL”. At each time, the operations of the steps SP
2
to SP
4
are repeated. Consequently, there is a problem in that a time required for erasing data is increased.
SUMMARY OF THE INVENTION
In order to solve the problems, it is an object of the present invention to provide a nonvolatile semiconductor storage device and a data erasing method thereof in which a time required for a data erasing operation is shortened.
According to a first aspect of the present invention, a nonvolatile semiconductor storage device includes a memory cell transistor and a control portion having a storage portion and serving to control a voltage pulse to be applied to the memory cell transistor. In a data erasing operation, the control portion gradually increases a pulse intensity and applies a writing pulse until data are written to the memory cell transistor before an erasing pulse is applied. The storage portion stores first information about a final pulse intensity of the writing pulse in a last data erasing operation. The control portion determines a starting value of a pulse intensity of the writing pulse in the data erasing operation based on the first information.
The control portion can determine the starting value of the pulse intensity of the writing pulse in a present data erasing operation to be a proper value based on the first information stored in the storage portion. Also in a data erasing operation to be carried out after a large number of data erasing operations have already been executed, accordingly, it is possible to decrease the number of times that the intensity of the writing pulse is to be increased and to shorten a time required for the data erasing operation.
According to a second aspect of the present invention, a nonvolatile semiconductor storage device includes a memory cell transistor and a control portion having a storage portion and serving to control a voltage pulse to be applied to the memory cell transistor. In a data erasing operation, the control portion gradually increases a
Shimizu Satoshi
Tomoeda Mitsuhiro
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