Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2003-07-01
2004-11-09
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185220
Reexamination Certificate
active
06816411
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-348932, filed Nov. 29, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device, and in particular, to a NAND type EEPROM and its deletion verification method.
2. Description of the Related Art
FIG. 1
is a circuit diagram showing a NAND type EEPROM (Electrically Erasable and Programmable Read Only Memory) as an example of a conventional non-volatile semiconductor storage device.
In the NAND type EEPROM, a NAND column is composed of memory cell transistors M
1
, M
2
, . . . , M
8
connected in series by connecting their sources and drains together. Word lines WL
1
, WL
2
, . . . , WL
8
are connected to gates of the memory cell transistors M
1
to M
8
, respectively.
Selection gate transistors ST
1
k
and ST
2
k
are connected to the opposite ends, respectively, of the NAND column. Selection gate lines SG
1
and SG
2
are connected to gates of the section gate transistors ST
1
k
and ST
2
k
, respectively. A bit line BL
k
is connected to the selection gate transistor ST
1
k
. A common source line SL is connected to the selection gate transistor ST
2
k
.
Further, a plurality of other NAND columns are arranged adjacent to the above NAND column. A selection gate transistor ST
1
k−1
or ST
1
k+1
is connected to one end of each of the plurality of NAND columns. Bit lines BL
k−1
and BL
k+1
are connected to the selection gate transistors ST
1
k−1
and ST
1
k+1
, respectively. Furthermore, a selection gate transistor ST
2
k−1
or ST
2
k+1
is connected to the other end of each of the plurality of NAND columns. A common source line S
1
is connected to the selection gate transistors ST
2
k−1
and ST
2
k+1
.
Furthermore, work lines WL
1
to WL
8
, the selection gate lines SG
1
and SG
2
, bit lines BL
k−1
, BL
k
, and BL
k+1
, and the common source line SL are provided with drive circuits
101
,
102
,
103
, and
104
, respectively.
With this configuration, adjacent cell transistors can share their sources and drains. This reduces the area of the transistors required for wiring. Thus, the NAND type EEPROM is characterized by its structure suitable for increased density. Further, the gate potentials of a large number of cell transistors can be simultaneously driven via the word lines WL
1
, WL
2
, . . . , WL
8
. Accordingly, data can be written to a large number of cell transistors at high speed or can be deleted or read from them at high speed.
FIG. 2
is a time chart showing the case in which a read operation is performed in the NAND type EEPROM.
A NAND type EEPROM composed of the series-connected cell transistors M
1
, M
2
, . . . , M
8
is characterized in that to read data from a selected cell transistor, non-selected cell transistors in the same NAND column must be turned on and have their data read. That is, the word lines WL to the non-selected cell transistors are provided with a sufficiently high potential as a read potential Vread. Only the word line WL to the selected transistor is provided with a determination potential VWLread used to determine whether the data is “0” or “1”.
At this time, if the provided read potential Vread is not sufficiently high, the non-selected cell transistors are turned off. Consequently, no cell currents flow regardless of the threshold voltage of the selected cell transistor. On the other hand, if the non-selected cell transistors are not sufficiently turned on, so that a read operation is performed while much channel resistance is remaining, then a cell current flows through the non-selected cell transistors to reduce their voltages. This increases the source potential of the selected cell transistor.
In such a case, a back bias effect or the effect of a decrease in the gate-source potential of the selected cell transistor inconveniently causes the threshold voltage of the selected cell transistor to be detected to have a value larger than its original one. Thus, with the NAND type EEPROM, the set value for the read potential Vread is a very important device specification.
Next,
FIG. 3
is a time chart for deletion verification in the NAND type EEPROM.
The deletion verification is an operation of determining whether or not a deleting operation has been successfully performed on all cell transistors, i.e. whether or not all cell transistors have negative threshold voltages. No negative potentials required for this determination can be output to the word lines of the NAND type EEPROM. Thus, an approach different from the above read method is required in order to determine whether or not the cell transistors have negative threshold values. First, a high potential is provided to the common source line SL to set the bit lines BL
k
at a predetermined low potential. Subsequently, by setting the potentials at the word lines WL and selection gates SG
1
and SG
2
in a selected NAND column, to appropriate values, a cell current flows from the common source line SL to the bit line BL
k
to charge this line BL
k
. As a result, the potential across the bit line BL
k
increases from a small value to provide a back bias effect. This makes it possible to detect a threshold voltage lower than the set word line potential (see, for example, Jpn. Pat. Appln. KOKAI Publication Nos. 7-161852 and 11-250676).
For the NAND type EEPROM, a minimum deletion size called a “block” is specified. Normally, a deleting operation is simultaneously performed on all cell transistors in the same NAND column. Subsequently, a read operation is performed by providing a sufficiently low determination potential VWLev to all word lines WL
1
to WL
8
in the NAND column. All cell transistors in the NAND column can have their threshold voltages determined at once by providing the same potential to all word lines. As a result, deletion verification can be carried out at high speed.
In the NAND type EEPROM, if a read operation is performed as described above, the effect of the previously described cell channel resistance is not negligible. In particular, if data is barely deleted from the cell transistors, the cell transistors have the maximum channel resistance. Accordingly, the back bias effect in the NAND column increases the threshold voltages to cause it to be determined that the deletion has not been completed yet. As a result, in a deletion verification operation, a deletion determination is made after the deletion has progressed sufficiently deeply (over-deletion).
Thus, it is still impossible to perfectly reliably determine the threshold voltages of cell transistors for which a deletion determination is to be made. However, this is a condition that makes the deletion determination stricter. In other words, it can be determined that the deletion is sufficient, on the basis of the results of the deletion verification.
However, as the structures of cell transistors become finer and finer, the over-deletion poses a critical problem because it may degrade cell reliability. Further, to suppress the degradation of a mis-write characteristic associated with the finer structures of cell transistors, local self boost (LSB) writes have been developed which utilize the cutoff characteristic of the cell transistors. Thus, it has been desirable to set a lower limit value for the threshold voltages of cell transistors after deletion.
Thus, two requirements have arisen for the threshold voltages of cell transistors after deletion. That is, the threshold voltages must be deep enough to avoid a non-deletion state even with a change in surrounding environments and must also be shallow enough to obtain a sufficient cutoff characteristic at a predetermined gate voltage. To meet these requirements, it is an important object to improve the accuracy with which the threshold voltages of cell transistors are determined after deletion.
BR
Arai Fumitaka
Matsunaga Yasuhiko
Yaegashi Toshitake
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