Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2001-11-13
2004-11-09
Nguyen, Viet Q. (Department: 2818)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S239000, C327S256000, C327S258000
Reexamination Certificate
active
06815994
ABSTRACT:
TECHNICAL FIELD
The invention relates to clocking circuits, and more particularly to circuits for generating a clock signal and a symmetrical complement of the clock signal.
BACKGROUND OF THE INVENTION
Clock signals are commonly used in digital circuits, including circuits used in memory devices, to control the timing at which various events occur. In some cases, a single clock signal is used. However, in other cases, it is necessary to use both the clock signal and the complement of the clock signal. The signals are typically generated by applying a clock signal to a phase splitter, which then generates a clock signal and its complement for use by the digital circuit.
It is important that the clock signal and its complement be symmetrical, i.e., the edges of both signals be substantially aligned and have the same slew rate. The clock signal and its complement generated by an ideal phase splitter would have a 50 percent duty cycle, equal rise and fall times and they would be exactly 180 degrees out of phase from each other. In practice, the ideal is rarely achieved for a variety of reasons, including process variations in the fabrication of the phase splitter. For example, for a CMOS process, one pass of the process may result in an inverter having a fast NMOS transistor and a slow PMOS transistor, and another pass of process may result in the inverter having a slow NMOS transistor and a fast PMOS transistor. As a result, the inverters will respond differently to incoming clock signal, and the respective clock signals generated by the inverters will not be symmetrical.
A conventional phase splitter
10
is illustrated in FIG.
1
. The phase splitter
10
includes two branches
12
,
14
, one of which generates a signal OUT and the other which generates its complement OUT*. The second branch
14
consists of three inverters
20
,
22
,
24
. Since there are an odd number of inverters in the second branch
14
, the complementary output signal OUT* is the complement of the input signal CLK, but delayed in time by the sum of the propagation delays through each of the inverters
20
-
24
.
The first branch
12
consists of two inverters
30
,
32
and a capacitor
34
connected to the output of the first inverter
30
. The size of the capacitor
34
is selected to delay the coupling of all of signals from the output of the first inverter
30
to the input of the second inverter
32
by an amount corresponding to the difference between the delay of the three inverters
20
-
24
and the two inverters
30
,
32
. As a result, the OUT signal and the OUT* signal are theoretically 180 degrees out of phase with each other. In practice, however, the OUT and OUT* may not be entirely symmetrical for several reasons. For example, although the capacitor
34
compensates for the delay of the extra inverter in the second branch
14
, it also reduces the slew rate of the signal applied to the input of the inverter
32
. As a result, the slew rate of the signal applied to the inverter
32
is substantially slower than the slew rate of the signal applied to the inverter
24
. This difference in slew rates causes the rise and fall times of the signals OUT and OUT* to differ substantially from each other.
Proposals have been made to modify the prior art phase splitter
10
shown in
FIG. 1
by dispensing with the capacitor
34
and instead adjusting the delay of each of the inverters
20
-
24
,
30
,
32
to achieve substantially the same result. More specifically, the inverters
20
,
24
and
30
may be designed so that the sum of the delays through the inverters
20
,
24
is equal to the delay through the inverter
30
. The inverters
22
and
32
are then designed so that they have equal propagation delays. As a result, the signals OUT and OUT* are, in theory, symmetrical. Again, in practice, the signals are anything but symmetrical for several reasons. For example, the inverters
20
,
24
must be relatively fast so that the sum of their delays is equal to the delay of the inverter
30
. The high-speed of the inverter
24
causes it to have a relatively high slew rate. In order for the slew rate of the OUT signal to match the slew rate of the OUT* signal, the transistors used in the inverter
32
must be relatively large. However, the inverter
30
must be fairly slow to achieve the required delay, and, as a result, its output signal has a relatively low slew rate. The low slew rate of the inverter
30
makes it all the more difficult for the output of the inverter
32
to match the output of the inverter
24
so that OUT and OUT* will have the same rise and fall times. If the slew rate of the inverter
24
is decreased to match the slew rate of the inverter
32
, the speed of the inverter
32
will also be reduced. As a result, is necessary to increase the speed of the inverter
20
by a commensurate amount, thereby making the inverter
20
very large. In addition to consuming a relatively large area of the substrate, making the inverter
20
large decreases the input impedance of the inverter
20
making it difficult for other circuits (not shown) to drive the inverter
20
.
A need therefore exists for a phase splitter that uses relatively little circuitry consuming relatively little area on a substrate that produces from a clock signal complementary signals that are substantially symmetrical in both phase and slew rate despite fabrication processing variations.
SUMMARY OF THE INVENTION
A phase splitter in accordance with the invention is operable to generate first and second complimentary output clock signals from an input clock signal. The phase splitter includes two branches receiving the input clock signal and generating the respective output clock signals. The first branch includes an even number of series connected inverters while the second branch includes an odd number of series connected inverters. In one aspect of the invention, an inverter is coupled between an output of an inverter in the first branch that is N number of inverters from the input clock signal and an output of an inverter in the second branch that is N+1 number of inverters from the input clock signal, where N is a positive integer, and where the added inverter's input is on the second branch and its output is on the first branch. Cross-coupling signals between the first and second branches in this manner provides delay but subsequently has increased the slew rate of the signal applied to an input of one of the inverters. In another aspect of the invention, a first pair of diode-connected transistors are coupled between an output of one of the inverters in the first branch that is M inverters from the input clock signal, and M+P inverters in either branch, to make the phase splitter substantially insensitive to process variations. M is a positive integer and P is positive even number. For the same reason, a second pair of diode-connected transistors are coupled between an output of one of the inverters in the second branch that is M inverters from the input clock signal, and M+P inverters in either branch.
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Chinnery, D.G. et al., “Achieving 550 MHz in an ASIC Methodology,” Department of EECS, University of California at Berkeley, 2001, 6 pages.
Friedman, Eby G., “Clock Distribution Networks in Synchronous Digital Integrated Circuits,” Invited Paper, IEEE, vol. 89, No. 5, May 2001, pp. 665-692.
Friedman, Eby G. et al., “Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI,” IEEE, vol. SC-21, No. 2, Apr. 1986, pp. 240-246.
IBM, “Method of Deskewing Data Pulses,” IBM Technical Disc
Brown David R.
Huber Brian W.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Viet Q.
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