Semiconductor device manufacturing: process – Utilizing varying dielectric thickness
Reexamination Certificate
2001-06-11
2004-06-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Utilizing varying dielectric thickness
C438S263000, C438S258000, C438S287000, C438S275000, C438S594000, C438S307000
Reexamination Certificate
active
06750159
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus having an insulated-gate type field-effect transistor, that is, a so-called MIS transistor, a manufacturing method therefor, a solid state image device having the so-called MIS transistor (hereinafter called as “MOS transistor”) to serve as a pixel and a manufacturing method therefor.
When a semiconductor apparatus having, for example, a MIS transistor is manufactured, processes using plasma are employed, for example, in a plasma etching process, an ion implanting process and a process for stripping a resist or the like.
Since the size of the semiconductor element has been reduced in recent years, the MOS transistor has more critically been damaged in the plasma process. Since the processes using plasma have been increased and the density of plasma has been raised considerably, the gate electrode has been charged up. Thus, an electric current flows through a gate insulation film, thus resulting in the gate insulation film being broken in the worst case.
When the thickness of the gate insulation film is reduced because of the reduction in the size of the element, a threshold voltages V
th
of the MIS transistors are dispersed excessively by the plasma damage. It leads to a fact that the operating voltage is lowered excessively and dispersion can not be tolerated.
To reduce the foregoing plasma damage, the density of charged particles has been lowered on the side of the plasma generating apparatus.
A method of reducing the plasma damage by the element itself will now be described.
An example of the basic pattern of a MIS transistor
61
is shown in FIG.
1
. The MIS transistor
61
is formed in an element-isolated active region
62
and a gate electrode
64
is formed over the active region
62
and a field region
63
formed around the active region
62
. Note that the active region
62
has a source and a drain (not shown) across the gate, the source and drain being, by a contact portion
65
, connected to upper wiring and so on.
To protect the MIS transistor
62
having the above-mentioned structure from being damaged during the plasma process, a method has been employed in which an area A′ of the portion of the gate electrode
64
formed on the field region
63
around the active region
62
is possibly minimized as compared with an area A of the portion of the gate electrode
64
formed on the active region
62
.
Since charges made incident on the gate electrode
64
are discharged to a silicon substrate through a thin portion, for example, the gate insulation film, the overall area of the gate electrode
64
which serves as an antenna is attempted to be reduced as much as possible.
However, the gate electrode is inevitably charged up because of the principle of the plasma process if plasma is used in the manufacturing process. Therefore, a tunnel current flows through a gate oxide film without exception, thus causing the potential to be raised until the leaked portion of the tunnel current and the incidental current from the plasma are balanced. Also electric currents flow undesirably.
As a result, fixed charges and surface levels are undesirably generated in the gate insulation film.
What is worse, the degree of generation of the fixed charges and the surface levels are dispersed among transistors.
If the above-mentioned phenomena arise once, heat treatment at a temperature exceeding 900° C. must be performed to solve the above defects.
The trend of finely forming the element has caused the heat treatment process to be performed at low temperatures. Thus, irregularity of the threshold voltage V
th
occurring due to the plasma damage is undesirably remained.
Also processes following the step for working the gate encounter discharge of incidental current of plasma for use in the ensuing flattening work and wiring work through the gate insulation film after the current has allowed to pass through the wiring layer made of Al or the like and the contact portion.
Moreover, discharge sometime takes place because of the difference in the potential between a polysilicon layer of the gate electrode and a resist formed on the polysilicon layer for the purpose of patterning the element.
So far as the plasma is employed to manufacturing the semiconductor apparatus, it is impossible to completely avoid the fact that the gate electrode is charged up and following leak currents flow from the gate insulation film to the substrate. As a result, dispersion of the threshold voltage V
th
of the transistor cannot easily be suppressed.
Since the level of an output signal with respect to the same input voltage is dispersed among transistors in an analog circuit or a circuit arranged to be operated at high speed comprising the MOS transistors due to the dispersion of the threshold voltage V
th
, the output signal must sometimes be corrected. Since delay of transmission is not the same among the transistors, design must be performed in such a manner that large voltages and sufficiently large operating margins can be realized. Thus, the size of the element has not satisfactorily been reduced.
On the other hand, solid state image devices having MOS transistors generally involve dispersion in the threshold voltage V
th
among the transistors. Devices of a 1-transistor for 1-pixel type, for example, a CMD (Charge Modulation Device) and a BCMD (Bulk Channel Modulation Device) and a 4-transistor pixel type device called an APS (Active Pixel Sensor) encounter dispersion of the threshold voltage V
th
in an image. In order to correct the dispersion of V
th
, a large-scaled circuit system is required. However, fixed-pattern noise cannot satisfactorily be suppressed even if the large-scaled circuit system is employed.
Although uniformity of the threshold voltages V
th
among all transistors is required, fluctuation of the parameters of the manufacturing conditions and influences of various damages including the above-mentioned plasma damage cause the fixed charges and the surface levels in the gate insulation film to be varied among pixels.
To remove the above-mentioned dispersion, the amount of charges on the gate electrode during the plasma process has been reduced by employing a contrivance of the structure of the manufacturing apparatus and the layout of the device pattern. For example, the device pattern is arranged to reduce the area on which plasma ions are made incident by minimizing the area of the gate electrode of the transistor formed on the field portion similarly to the above-mentioned MIS transistor.
However, the solid state image device having a structure that one pixel is formed by one transistor suffers from dispersion in the threshold voltage V
th
being left although no gate electrode exists on the field portion. That is, employment of the above-mentioned contrivance cannot completely overcome the problem of unsatisfactory quality of the image caused from the damage by the charge of plasma.
Therefore, it has been considered that charge on the gate electrode cannot furthermore be avoided. In order to overcome the above-mentioned problem, charge on the gate electrode has been canceled by the structure of the circuit and the system. Thus, the size of the device cannot be reduced and a system for canceling the charge becomes too complicated and the scale of the system cannot be reduced. As a result, the cost of the device cannot be reduced.
SUMMARY OF THE INVENTION
In view of such aspects, it is an object of the present invention to provide a semiconductor apparatus and a manufacturing method therefore arranged such that dispersion of threshold voltages V
th
of transistors is reduced to inhibit generation of fixed charges and surface levels in a gate insulation film to stabilize the operation of the semiconductor apparatus and a solid state image device which is capable of suppressing fixed pattern noise and therefore improving the image quality and a manufacturing method therefor.
A semiconductor apparatus according to the present invention has a structure that a gate electrode of an MIS transist
Niebling John F.
Pompey Ron
Sonnenschein Nath & Rosenthal LLP
LandOfFree
Semiconductor apparatus, manufacturing method therefor,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor apparatus, manufacturing method therefor,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor apparatus, manufacturing method therefor,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3333853