Virtual memory mapping method and system for address translation

Details Virtual memory mapping method and system for address translation Virtual memory mapping method and system for address translation

1995-12-12

1998-01-13

Downs, Robert W.

395417, 395418, 395419, 3954211, G06F 1200, G06F 1202, G06F 926, G06F 932

Patent

active

057087903

ABSTRACT:
A method and system for address translation mapping of logical partitions for address translation buffer entries in a data processing system is provided. The method comprises receiving a logical address for a memory reference to a selected logical partition of a plurality of logical partitions of a particular block of virtual memory, wherein the block of virtual memory is divided into the plurality of logical partitions, and wherein the logical address includes a plurality of logical partition selection bits selecting the selected logical partition from among the plurality of logical partitions. If the selected logical partition is valid in real memory, as indicated by a logical partition valid bit associated with the selected logical partition, a physical address for the memory reference in the selected logical partition is compiled from an entry of an address translation buffer that is associated with the particular block of virtual memory, wherein the logical partition valid bit is one of a plurality of logical partitions valid bits contained in the entry associated with the particular block of virtual memory, the plurality of logical partition valid bits being associated with the plurality of logical partitions. Thereafter, the memory reference within the selected logical partition is retrieved at the compiled physical address.

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