Method of fabricating shallow trench isolation structure

Details Method of fabricating shallow trench isolation structure Method of fabricating shallow trench isolation structure

2003-01-28

2004-12-07

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000, C438S435000, C438S692000, C438S717000

Reexamination Certificate

active

06828208

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method of fabricating an electrically insulating structure. More particularly, the present invention relates to a method of fabricating a shallow trench isolation (STI) structure.
2. Description of Related Art
Due to the rapid increase in the level of integration, design rules for fabricating semiconductor devices have decreased to a line width of about 0.18 &mgr;m or lower. Conventional electrical insulation structure such as silicon oxide layer can no longer be produced through a local oxidation (LOCOS) process. To produce viable electrical insulation to isolate devices, a method of fabricating shallow trench isolation structures has been developed.
A shallow trench isolation structure is conventionally fabricated by conducting a high-density plasma chemical vapor deposition (HDPCVD) process so that silicon oxide material is deposited into a trench. Since a HDPCVD process has a low degree of conformity, excessive amount of silicon oxide material has to be deposited and then chemical-mechanical polished to remove the excess material above the trench. However, density of distribution of the trenches on a substrate may vary. Due to differences in pattern density, material may be removed from regions with high trench density faster than other regions having a lower trench density. Ultimately, dishing of upper surface may occur in regions having a lower trench density leading to big variation in device reliability.
Conventionally, a reverse masking process is often used to resolve dishing problem.
FIG. 1
is a schematic cross-sectional view of a substrate in a region with a sparse distribution of trenches. As shown in
FIG. 1
, a substrate
100
with a pad oxide layer
102
, a mask layer
104
and a trench
106
thereon is provided. A high-density plasma chemical vapor deposition (HDPCVD) process is conducted to form a silicon oxide layer
108
to fill the trenches
106
and cover the mask layer
104
. Thereafter, a photoresist layer (not shown) is formed over the silicon oxide layer
108
. A yellow light processing is next conducted to form a pattern in the high-density regions and a reverse mask
114
in the low-density regions of the photoresist layer.
After patterning the photoresist layer, the silicon oxide layer
108
is etched using the photoresist layer and the reverse mask
114
as a mask until the upper surface of the mask layer
104
is exposed. Thereafter, the photoresist layer and the reverse mask
114
are removed so that the original low-density pattern region reverses into a high-density pattern region. A chemical-mechanical polishing operation is carried out to remove the silicon oxide layer until the upper surface of the silicon nitride layer is exposed. Finally, the silicon nitride layer and the pad oxide layer are removed to form a shallow trench isolation (STI) structure.
However, as devices continue to miniaturize, the aforementioned reverse masking process of fabricating shallow trench isolation structure is increasingly infeasible because of a narrowing of processing window. Moreover, any misalignment of the patterning mask may lead to the production of recesses
114
. When the mask layer
104
is used as an etching stop layer in etching the silicon oxide layer
110
, the recesses
114
may serve as entry points into the mask layer
104
so that the mask layer
104
may be etched through leading to over-etching. Consequently, the silicon substrate may be structurally damaged.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a method of fabricating a shallow trench isolation (STI) structure that can increase the process window in the fabrication of a reverse mask using a yellow light processing.
A second object of this invention is to provide a method of fabricating a shallow trench isolation (STI) structure that can prevent any damage to an underlying silicon substrate due to over-etching in an insulation layer etching process.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench and the third trench has a width smaller than the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are removed to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.
In this invention, a conformal cap layer is formed over the insulation layer. Hence, width of the trench above the insulation layer is reduced through the trench formed in the cap layer. Consequently, process window for fabricating a reverse mask over the trench is increased. Hence, the reverse mask is able to cover the trench entirely and prevents the formation of a recess at the junctions between the reverse mask and the trench.
Furthermore, in the absence of recess at the junction between the reverse mask and the trench, the process of etching the insulation layer is able to stop right at the interface with the mask layer. Since over-etching through recesses is prevented, the underlying silicon substrate is saved from any harmful effects.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6043133 (2000-03-01), Jang et al.
patent: 6436789 (2002-08-01), Sawamura
patent: 6531265 (2003-03-01), Mei et al.
patent: 6638866 (2003-10-01), Cheng et al.

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