Telecommunications – Transmitter and receiver at separate stations – Plural transmitters or receivers
Reexamination Certificate
2002-06-20
2004-11-16
Vuong, Quochien B. (Department: 2685)
Telecommunications
Transmitter and receiver at separate stations
Plural transmitters or receivers
C455S127100, C455S127200
Reexamination Certificate
active
06819938
ABSTRACT:
FIELD OF THE INVENTION
The disclosed subject matter is directed generally to power control in a wireless communication device and, more particularly, to a system and method for calibration of open-loop power control in a wireless communication device.
BACKGROUND OF THE INVENTION
Wireless communication devices are widely used throughout the world. Such wireless devices use radio frequency components, including transmitters and receivers. Proper operation of wireless devices requires the careful calibration of the transmitter and receiver sections. This is particularly important in some wireless communications schemes, such as code division multiple access (CDMA) technology where multiple users are transmitting simultaneously on the same frequency.
As is known in the art, CDMA technology assigns different pseudo noise (PN) codes to each wireless device. The PN codes are mathematically uncorrelated to each other such that one CDMA wireless device cannot decode the radio frequency (RF) signal intended for another CDMA device. As a result, a signal transmitted from one CDMA wireless device appears as noise to other CDMA devices operating at the same frequency and in the same geographic region. Thus, it is desirable to minimize transmitted power for each CDMA device in order to reduce the noise effects on other CDMA devices. Therefore, proper calibration of each CDMA device is important for satisfactory operation of the overall CDMA system.
A simplified block diagram of the receiver portion of a CDMA device is illustrated in the function block diagram of FIG.
1
. The operation of the wireless device
10
illustrated in the functional block diagram of
FIG. 1
is known to those of ordinary skill in the art and thus need not be described in great detail herein. Radio signals are detected by an antenna
12
and coupled to an RF stage
14
. The RF stage
14
may include a number of different components, such as amplifiers, tuning circuitry, filters, and the like. For the sake of brevity, those various components are illustrated in
FIG. 1
as the RF stage
14
. The output of the RF stage
14
is coupled to an intermediate frequency (IF) stage
16
. The RF stage
14
and IF stage
16
amplify the signal detected by the antenna
12
and shift the frequency from RF frequencies down to an intermediate frequency.
A variable gain amplifier (VGA)
18
receives the signal from the IF stage
16
and amplifies the signal to a desired level. As will be described in greater detail below, the variable gain amplifier has a variable gain input V
CONT
which sets the level of amplification. Although the VGA
18
is illustrated as a single component, a typical implementation often uses multiple stages of amplification to provide the necessary gain. However, these are engineering implementations within the skill of the design engineer. For the sake of simplicity, the multiple gain stages are illustrated in
FIG. 1
as the VGA
18
.
The output of the VGA
18
is coupled to a demodulator
19
. The demodulator
19
comprises quadrature mixers
20
and
22
. The quadrature mixer
20
is mixed with a local oscillator ILO while the quadrature mixer
22
is mixed with the local oscillator QLO. The output of the quadrature mixers
20
and
22
are taken for further processing in a conventional manner to produce the voice signal. However, the presently disclosed subject matter is directed to control of amplifiers and is not directly related to the actual processing of the received signals to produce the audio data.
The output of the quadrature mixers
20
and
22
are also coupled to low-pass filters
24
and
26
, respectively, and subsequently coupled to inputs of respective analog-to-digital converters (ADC)
28
and
30
. To efficiently utilize the dynamic range of the ADCs
28
and
30
, the device
10
is designed to control the gain of the VGA
18
so as to produce a fixed power level at the inputs of the ADCs
28
and
30
.
The outputs of the ADCs
28
and
30
are provided to an automatic gain control (AGC) loop
31
that ultimately will control the gain of the VGA
18
. The outputs of the ADCs
28
and
30
are combined in a summing circuit
32
and provided to a log circuit
34
. The log circuit
34
converts the signal from a linear form to a logarithmic form to thereby permit control of the VGA
18
in decibels (dB). The output of the log circuit
34
is combined with a control voltage P
REF
in an adder
36
. The control voltage P
REF
is a control setpoint for the AGC loop
31
.
The output of the adder
36
is integrated by an integrator
38
and provided as an input to a linearizer
40
. The integrator
38
averages the control signal from the adder
36
and controls the response time of the AGC loop
31
through the selection of an integration time. It is also possible to control the bandwitdth of the AGC loop
31
by varying the gain of the integrator
38
. An increase of the gain of the integrator
38
causes a corresponding increase in the bandwidth of the AGC loop
31
. So long as the VGA
18
is properly linearized, the output of the integrator
38
is a linear function of the power-in (P
IN
) detected by the RF stage
14
and IF stage
16
. The output of the integrator
38
is also an indication of the strength of the received signal. The signal is generally described in the wireless communication industry as a received signal strength indicator (RSSI).
Although the RSSI is an indicator of received signal strength, the signal itself cannot be used directly to control the gain of the VGA
18
because of the inherent nonlinearities of the variable gain input. As will be discussed in greater detail below, the linearizer
40
compensates for non-linearities in the control voltage versus gain characteristics of the VGA
18
. The output of the linearizer
40
is provided to a digital-to-analog circuit (DAC)
42
. The output of the DAC
42
is the control voltage V
CONT
that controls the gain of the VGA
18
.
As noted above, it is desirable to produce fixed level inputs for the ADCs
28
and
30
. The gain of the VGA
18
is controlled by the AGC loop
31
to provide the desired level at the inputs of the ADCs
28
and
30
.
FIG. 2
illustrates the ideal gain of the VGA
18
versus input power produced by the IF stage
16
.
FIG. 2
illustrates the ideal linear relationship between gain and power in (P
IN
). In an ideal situation, if P
IN
decreases, the gain of the VGA
18
increases by the same amount such that the power provided to the ADCs
28
and
30
is constant. Unfortunately, the variable gain input versus gain of the VGA
18
is not linear.
FIG. 3
illustrates the relationship between the control voltage V
CONT
and the gain of the VGA
18
. The ideal curve shows a linear relationship between the control voltage V
CONT
and the gain. However, process variations and design limitations of the VGA
18
make it virtually impossible to achieve ideal linear relationship.
FIG. 3
also illustrates the actual relationship between the control voltage V
CONT
and gain of the VGA
18
. The actual curve has been somewhat exaggerated to illustrated the nonlinearity between the control voltage V
CONT
and gain. Because of this inherent nonlinearity, it is necessary to utilize the linearizer
40
to compensate for differences between the actual control voltage curve and the ideal voltage curve.
It should be noted that the non-linearity described herein refers to the nonlinear relationship between the voltage control V
CONT
and the actual gain of the VGA
18
. The relationship between the input and output of the VGA
18
is highly linear. That is, the output of the VGA
18
is a highly accurate amplified version of the input. The non-linearity referred to herein is the nonlinear relationship between the voltage control input and the gain setting of the VGA
18
.
As noted above, the linearizer
40
is used to compensate for nonlinearities in the gain control of the VGA
18
. A number of different known techniques may be used to implement the linearizer
40
. One such technique utilizes piece-wise li
Brown Charles
Chow C.
Kordich Donald
Qualcomm Incorporated
Vuong Quochien B.
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