Method of making sub-lithographic sized contact holes

Details Method of making sub-lithographic sized contact holes Method of making sub-lithographic sized contact holes

2003-08-14

2004-08-17

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S094000, C438S096000, C438S097000, C438S098000, C438S666000, C438S667000, C257S002000, C257S003000, C257S004000, C257S005000

Reexamination Certificate

active

06777260

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to the formation of sub-lithographic sized contact holes in which electrical devices are formed.
BACKGROUND OF THE INVENTION
In the fabrication/manufacture of devices on a semiconductor substrate, such as certain circuits or memory devices, it is often desirable to form extremely small contact holes in which such circuits or memory devices are formed. For example, phase change memory devices have been known for some time. These devices use materials that can be electrically switched (programmed) between different structured states that exhibit different electrical read-out properties. One such phase change memory material is chalcogenide, which is programmable between a generally amorphous state (that exhibits a relatively high resistivity) and a generally crystalline state (that exhibits a relatively low resistivity). The chalcogenide material is programmed by heating the material, whereby the amplitude and duration of the heating dictates whether the chalcogenide is left in an amorphous or crystallized state. The high and low resistivities represent programmed “1” and “0” values, which can be sensed by then measuring the resistivity of the chalcogenide material.
FIG. 1A
illustrates a memory cell employing chalcogenide phase change memory material. The memory cell includes a layer of chalcogenide
2
disposed between a pair of electrodes
4
/
6
, which are surrounded by thermal and electrical insulator material
8
. One of the electrodes (in this case the lower electrode
4
) has an increased resistivity making it a thermal heater that heats the chalcogenide layer
2
when an electrical current is passed through the electrodes
4
/
6
(and through the chalcogenide layer
2
).
FIG. 1A
, for example, shows the chalcogenide
2
in its crystallized form in which the material is highly conductive, and provides a low resistance between electrodes
4
/
6
. When heated by electrode
4
by an amorphousizing thermal pulse (short thermal pulse with rapid cooling so chalcogenide material amorphousizes without time to crystallize), at least a portion
10
of the chalcogenide layer
2
is amorphousized, as shown in
FIG. 1B
, which increases the electrical resistance of the chalcogenide material. The chalcogenide
2
can by crystallized back to its lower electrical resistance state by applying a crystallization thermal pulse (longer thermal pulse that allows chalcogenide to crystallize). The electrical resistance of this memory cell can be read using a small electrical current that does not generate enough heat to reprogram the chalcogenide material.
There is a constant need to shrink down the size of the memory cells. The power needed to program such memory cells is generally proportional to the cross-sectional area and volume of the memory material being amorphousized/crystallized. Thus, reducing the size and volume of the memory material used in each cell reduces the electrical current and power consumption of the memory device. Smaller sized memory cells also reduces the overall size of memory cell arrays, and provides more space between memory cells for greater thermal isolation.
Phase change memory devices are typically made using conventional photo lithography processing, whereby photo resistant masking material is disposed over one or more layers of insulation material. A masking step is performed to selectively remove the photo resistant masking material from certain regions (i.e. hole locations) of the insulation material, which are left exposed. An etch process follows, which etches away the exposed portions of the insulation material, forming contact holes therein. The programmable memory material and usually one or both electrodes are formed in the contact holes. Therefore, the size of the contact holes dictates the size and volume of the memory material used by the memory cells.
In order to minimize memory cell size, and achieve the advantages of reducing the size and volume of programmed memory material, it is imperative to maximize the resolution of the photo lithography process being used to make such memory cells. Unfortunately, conventional photo lithography techniques simply do not have a resolution that has been scaling down fast enough to reliably produce contact holes of the desired size. Holes in photo resist masking material can simply be made only so small.
One solution has been to form spacers inside the holes before the memory material blocks are formed, which effectively reduces the width dimensions of the contact holes (see for example U.S. Pat. No. 6,511,862). However, as the desired contact hole widths become extremely small (i.e. on the order of 10 nm), it can be difficult to control spacer formation to precisely and repeatedly form contact holes of the desired size.
There is a need for a technique to form sub-lithographic sized contact holes that have smaller dimensions than that producible by conventional photo lithographic processes.
SUMMARY OF THE INVENTION
The present invention is a method for forming a contact hole in a semiconductor device by forming a first material over a substantially horizontal surface of a semiconductor substrate, forming an etch mask over the first material where the etch mask includes at least a first trench and a second trench formed therein and where a through-hole extends entirely through the etch mask where the first and second trenches intersect each other and exposes an area of the first material, and performing an etch process on the exposed area of the first material via the through-hole to form a contact hole in the first material.
In another aspect of the present invention, the method includes forming a first material over a substantially horizontal surface of a semiconductor substrate, forming an etch mask over the first material where the etch mask includes a plurality of first trenches and a plurality of second trenches formed therein and where through-holes extend entirely through the etch mask where the first trenches intersect with the second trenches and expose areas of the first material, and performing an etch process on the exposed areas of the first material via the through-holes to form contact holes in the first material.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended FIGURES.


REFERENCES:
patent: 5395797 (1995-03-01), Chen et al.
patent: 5468652 (1995-11-01), Gee
patent: 5759911 (1998-06-01), Cronin et al.
patent: 6228747 (2001-05-01), Joyner
patent: 6229169 (2001-05-01), Hofmann et al.
patent: 6461888 (2002-10-01), Sridhar et al.
patent: 6511862 (2003-01-01), Hudgens et al.
patent: 6514805 (2003-02-01), Xu et al.
patent: 2002/0119592 (2002-08-01), Oswald et al.
patent: 2003/0221718 (2003-12-01), Kubo et al.
patent: 2004/0042329 (2004-03-01), Dennison

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