Memory vacancy management apparatus and line interface unit

Details Memory vacancy management apparatus and line interface unit Memory vacancy management apparatus and line interface unit

1999-09-29

2004-12-14

Hsu, Alpus H. (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395100, C370S236200

Reexamination Certificate

active

06831920

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory vacancy management apparatuses and line interface units, and more particularly to a memory vacancy management apparatus for managing vacant addresses of a memory and to a line interface unit which uses such a memory vacancy management apparatus.
Usually, memories are used in various kinds of apparatuses and equipments used in the field of communication, typified by switching systems, transmission units and terminal equipments. Such memories have various structures and functions. For example, a RAM coupled to a microprocessor bus may be used for a control unit or signal control. In addition, a memory may be provided in a channel system to process the communication data itself, such as a First-In-First-Out (FIFO) which absorbs a phase error of a clock and an elastic memory.
2. Description of the Related Art
Amongst the above described memories, there is a memory which is provided with a function of searching vacant addresses which are not in use.
FIG. 1
is a system block diagram showing an example of a conventional memory having the vacant address searching function. The memory includes a memory cell part (MCELL)
1
, a vacant address management table (VTBL)
2
, an access controller (ACTL)
3
, and a vacant address searcher (VSCH)
4
which are connected as shown in FIG.
1
.
The memory cell part
1
stores external data written therein. The vacant address management table
2
has the same address structure as the memory cell part
1
, and contains information which indicates whether or not data are stored at corresponding addresses of the memory cell part
1
, that is, whether or not the corresponding addresses of the memory cell part
1
are “in use” or “vacant”. The access controller
3
controls access, that is, read and write, with respect to the memory cell part
1
. In addition, the access controller
3
controls updating of the contents of the vacant address management table
2
. The vacant address searcher
4
searches for a next vacant address to which the writing is possible, based on the contents of the vacant address management table
2
. The access controller
3
receives a signal ACADR which indicates the address, a write data WDATA, a write request WREQ, and a read request RREQ, and outputs read data RDATA.
FIG. 2
is a flow chart for explaining the operation of the conventional memory shown in FIG.
1
. In
FIG. 2
, a step initializes the vacant address management table
2
and the memory cell part
1
. When the initializing of the vacant address management table
2
and the memory cell part
1
ends, a step S
2
decides whether or not an access is made from outside the memory. If the decision result in the step S
2
is YES, a step S
3
decides whether the access is a read or a write.
If the access is the write, a step S
4
decides whether or not the vacant address searcher
4
outputs a signal FULL which indicates that the memory cell part
1
is full. If the decision result in the step S
4
is NO, a step S
5
writes the write data WDATA into the memory cell part
1
at an address corresponding to a vacant address VADR output from the vacant address searcher
4
, and at the same time, sets “in use” in the vacant address management table
2
at the corresponding address.
On the other hand, if the access is the read in the step S
3
, a step S
6
decides whether or not an address ACADR of the memory cell part
1
is in use. If the decision result in the step S
6
is YES, a step S
7
reads the data written at the address ACADR, and sets “vacant” in the vacant address management table
2
at an address corresponding to the address ACADR.
Next, in a step S
8
, the vacant address searcher
4
carries out a vacancy search process by making a reference to the vacant address management table
2
. A step S
9
decides whether or not a vacant address is found. If the decision result in the step S
9
is YES, a step S
10
sets the vacant address found as the vacant address VADR. On the other hand, if the decision result in the step S
9
is NO, a step S
11
outputs the signal FULL which indicates that there is no vacant address in the vacant address management table
2
.
According to this conventional memory, the vacant address searcher
4
constantly searches for the vacant address within the memory cell part
1
, and the vacant address found as a result of the search is notified to the access controller
3
. Here, the vacant address refers to the address where no valid data is written in the memory cell part
1
from outside the memory. Accordingly, when an external circuit which uses the memory needs to buffer the data into the memory, it is first necessary to check whether or not the signal FULL is output from the memory. If no signal FULL is output from the memory, the data to be buffered is input to the memory as the write data WDATA, while making the write request WREQ to the memory active.
By the operation described above, the write data WDATA which is to be buffered in the memory is stored at the address of the memory cell part
1
indicated by the vacant address VADR. Hence, the external circuit which uses the memory does not have to be aware of which addresses are vacant. After the write data WDATA is written at the address which is indicated by the vacant address VADR, the address is no longer “vacant”, and thus, at the same time as writing the write data WDATA into the memory cell part
1
, the access controller
3
writes a flag which indicates “in use” at the corresponding address of the vacant address management table
2
. Furthermore, a trigger for starting the search is issued from the access controller
3
to the vacant address searcher
4
in order to search for the new vacant address VADR.
On the other hand, when the access to the memory is the read, the external circuit which uses the memory inputs the signal ACADR to the access controller
3
, and then makes the read request RREQ active. As a result, the read data RDATA indicates the content of the memory cell part
1
at the address specified by the signal ACADR. In addition, since the read address of the memory cell part
1
is no longer “in use”, the access controller
3
simultaneously writes the flag which indicates “vacant” at the corresponding address of the vacant address management table
2
. By updating the vacant address management table
2
, the vacancy state of the memory cell part
1
also changes, but it is unnecessary to trigger the start of the search in this case, because it remains unchanged that the vacant address VADR already found by the vacant address searcher
4
is “vacant”.
In a case where the signal FULL is output before the read is carried out with respect to the memory, the vacant address VADR does not indicate a valid vacant address, and it is necessary in this case to trigger the start of the search. In this case, it is clear that only the address just read is vacant, there is no need to search for the vacant address, and it is sufficient to simply copy the signal ACADR as the vacant address VADR.
Conventionally, the memory having the vacant address search function is generally realized by a software approach, that is, the entire memory or a part excluding a memory part corresponding to the memory cell part
1
is realized by software. In this case, a microprocessor or the like is used to carry out the vacant address search operation of the vacant address searcher
4
.
FIG. 3
is a diagram showing the construction of the memory using a microprocessor. In
FIG. 3
, those parts which are the same as those corresponding parts in
FIG. 1
are designated by the same reference numerals.
FIG. 3
shows a case where a microprocessor
10
is coupled to another circuit via a processor bus
13
.
A RAM
11
which forms the memory includes the memory cell part (main buffer part)
1
, the vacant address management table
2
, the access controller (access control program)
3
, and the vacant address searcher (VTBL search program)
4
. An input/output (I/O) port
12
is coupled to th

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