Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-29
2004-06-08
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S226000, C365S189090, C365S185050, C365S185270, C327S530000
Reexamination Certificate
active
06747897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor charge pump circuit for generating a voltage which is higher than a supply voltage or a negative voltage, and a nonvolatile semiconductor memory device including such a semiconductor charge pump circuit.
2. Description of the Related Art
Conventionally, semiconductor memories, for example, EEPROMs (Electrically Erasable and Programmable Read Only Memories) and flash memories, require a voltage which is higher than a supply voltage or a negative voltage for read/write/erase operations. One of the following two methods are used to generate such a voltage: (i) applying an external voltage; and (ii) pumping a supply voltage by a charge pump circuit provided in a chip. Recently, the method of pumping a supply voltage by a charge pump circuit provided in a chip has become the method of choice since chips mostly include only one power supply today.
A basic principle of operation of a charge pump circuit will be described.
FIG. 9
shows a change in the voltage of a capacitor C
1
used for pumping. In an initial state, a first end of the capacitor C
1
is supplied with 0 V, and a second end of the capacitor C
1
is supplied with a supply voltage Vcc.
When the potential of the first end is changed from 0 V to the supply voltage Vcc, the supply voltage Vcc of the second end is doubled to 2×Vcc. Namely, the voltage of the second end is pumped to 2×Vcc. This is represented by expression (1).
Q
1
=
C
×Vcc
Q
2
=
C
×(2Vcc−Vcc)=
C
Vcc (1)
In expression (1), letter C represents the capacitance of the capacitor C
1
. Expression (1) represents Q
1
=Q
2
; i.e., “conservation of charge”. The above-described basic principle of operation of a charge pump circuit can be applied to an LSI circuit. One generally known charge pump circuit for an LSI is a Dickson-type charge pump circuit.
FIG. 10
shows a representative configuration of a conventional Dickson-type charge pump circuit. In the example shown in
FIG. 10
, the conventional Dickson-type charge pump circuit includes five n-type MOS (metal-oxide-semiconductor) transistors D
0
through D
4
and four capacitors C
1
through C
4
.
A basic pump cell of the Dickson-type charge pump circuit shown in
FIG. 10
includes, for example, one capacitor C
1
and one n-type MOS transistor D
1
, which are surrounded by a dashed line in FIG.
10
. Four such basic pump cells, each including one capacitor (C
1
, C
2
, C
3
, C
4
) and one n-type MOS transistor (D
1
, D
2
, D
3
, D
4
), are connected in series so as to form the charge pump circuit.
The first-stage transistor D
0
has a drain D and a gate G which are both connected to an output end of a power supply (supply voltage Vcc: for example, 3V). The transistor D
0
acts as a backflow preventing valve for preventing an electric current from backflowing from a node N
1
toward the power supply Vcc. The node N
1
is connected to a source of the transistor D
0
and has a pumped-up voltage.
The charge pump circuit receives clock signals CLK
1
and CLK
2
as input signals. The clock signal CLK
1
is input to the capacitors C
1
and C
3
, and the clock signal CLK
2
is input to the capacitors C
2
and C
4
.
FIG. 11
is a timing diagram illustrating waveforms of the clock signals CLK
1
and CLK
2
.
As shown in
FIG. 11
, the clock signals CLK
1
and CLK
2
each have an amplitude which is equal to the supply voltage Vcc. The clock signals CLK
1
and CLK
2
have opposite phases to each other. For example, when the clock signal CLK
1
is at the supply voltage Vcc, the clock signal CLK
2
is at 0 V. When the clock signal CLK
1
is at 0 V, the clock signal CLK
2
is at the supply voltage Vcc.
Returning to
FIG. 10
, a voltage pumped by the charge pump circuit is output from an output node Nout. Although not shown in
FIG. 10
, the output node Nout is connected to, for example, a regulator or a smoothing capacitor. A voltage which is pumped by the charge pump circuit (a positive high voltage in this example) is output to, for example, the regulator through the output node Nout.
FIG. 12
is a schematic cross-sectional view of an n-MOS transistor.
As shown in
FIG. 12
, a flash memory generally uses a p-type substrate. The n-type MOS transistor is formed as follows. The p-type substrate is provided with a reference voltage Vss (0 V). A source region S (n+) and a drain region D (n+) are formed in the p-type substrate with a prescribed distance therebetween. A gate G is formed on an area of the p-type substrate which is interposed between the source region S and the drain region D. The p-type substrate and the gate region G have an insulating layer therebetween. A plurality of n-type MOS transistors having such a structure are connected in series so as to form a charge pump circuit as shown in FIG.
10
.
FIG. 13
is a timing diagram illustrating ideal waveforms of nodes N
1
through N
4
of a Dickson-type charge pump. As shown in
FIG. 10
, the node N
1
is provided between the n-type MOS transistor D
0
and the N-type MOS transistor D
1
, the node N
2
is provided between the N-type MOS transistor D
1
and the N-type MOS transistor D
2
, the node N
3
is provided between the n-type MOS transistor D
2
and the N-type MOS transistor D
3
, and the node N
4
is provided between the N-type MOS transistor D
3
and the N-type MOS transistor D
4
.
In an initial state where the capacitors C
1
through C
4
do not have any charge accumulated therein and the clock signals CLK
1
and CLK
2
are 0 V, voltages VN
1
through VN
4
of the nodes N
1
through N
4
are represented by expression (2).
VN
1
=Vcc−Vth
VN
2
=Vcc−2Vth
VN
3
=Vcc−3Vth
VN
4
=Vcc−4Vth (2)
As can be appreciated from expression (2), each time the charge is transferred by an N-type MOS transistor so as to pump up the voltage of anode, the pumped-up voltage of the node is reduced by the threshold voltage Vth of an N-type MOS transistor (for example, about 0.6 V).
As shown in
FIG. 13
, when the voltage of the clock signal CLK
1
is changed from 0 V to Vcc, the voltage of the node N
1
is changed to 2Vcc−Vth, and an output voltage of (2Vcc−Vth)−Vth−Vb is transferred by the N-type MOS transistor D
1
from the source of the N-type MOS transistor D
1
to the node N
2
. “Vb” represents a voltage drop of the transferred potential, the voltage drop caused by a substrate biasing effect. The voltage drop Vb increases in proportion to the source—substrate voltage V
BS
.
When the voltage of the clock signal CLK
2
is changed from 0 V to supply voltage Vcc, the voltage of the node N
2
is changed from 2Vcc−2Vth−Vb to 3Vcc−2Vth−Vb.
The above-described operation is repeated up to the node N
4
as shown in
FIG. 13
, and the resultant voltage is output as an output voltage Vout from the charge pump circuit.
The output voltage of such a Dickson-type charge pump circuit (corresponding to the voltage of a node Nout) is represented by expression (3) as described in, for example, “Ki-Hwan Choi et al., 1997 Symposium on VLSI Circuits Digest of Technical Papers, 1997”.
Vout
(
conventional
)
=
Vcc
-
Vth
(
0
)
⎵
(
a
)
+
∑
i
=
1
n
{
(
a
)
Vcc
-
Vth
(
i
)
}
⎵
(
b
)
(
3
)
In expression (3), Vth(
0
) represents a threshold voltage of the N-type MOS transistor D
0
(for example, Vth=0.6 V), and Vth(i) represents a threshold voltage of the n′th N-type MOS transistor. Term (a) of expression (3), i.e., “Vcc−Vth(
0
)” is practically “1”. “i” is a natural number.
Vth(i) represents a threshold obtained in consideration of the substrate biasing effect. The larger the difference between the voltage of the source and the voltage of the substrate (in this example, the voltage of the p-well) is, the larger the value of Vth(i) is. In expression (3), Vth and Vb are independently represented (Vth+Vb≈Vth). In a structure including mul
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Yoha Connie C.
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