Image analysis – Image compression or coding – Interframe coding
Reexamination Certificate
2001-04-30
2004-08-24
Johnson, Timothy M. (Department: 2625)
Image analysis
Image compression or coding
Interframe coding
C382S239000, C382S233000, C382S243000, C375S240080
Reexamination Certificate
active
06782134
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a transmission apparatus for video information, a transmission system for video information and a transmission method for video information.
The application field of computers is growing wider in recent years. Under these conditions, a computer which is divided into a part (referred to as “first terminal apparatus”) which includes a CPU (central processing unit) or the like, and a part (referred to as “second terminal apparatus”) which includes a display part for the video (or a display part and an input part) is in demand by the market.
FIG. 10
is a conceptual diagram of a computer which has a first terminal apparatus and a second terminal apparatus.
In
FIG. 10
the first terminal apparatus which includes a CPU is denoted as
1001
, the second terminal apparatus which includes a display part and a pen input part is denoted as
1002
, a conventional PC (abbreviation of personal computer which has a CPU and a display part) is denoted as
1003
, a docking station is denoted as
1004
, a keyboard is denoted as
1005
and a display part is denoted as
1006
. The first terminal apparatus
1001
has a CPU
1011
and a wireless communication part
1012
. The second terminal apparatus
1002
has a display and pen input part
1021
and a wireless communication part
1023
. The user can input an instruction into a computer by touching the display and pen input part
1021
with a pen
1022
.
Video information generated in the CPU
1011
of the first terminal apparatus
1001
is transmitted from the wireless communication part
1012
. The wireless communication part
1023
of the second terminal apparatus
1002
receives the video information and transmits it to the display and pen input part
1021
. The display and pen input part
1021
displays the inputted video information.
When the user inputs, with a pen
1022
, an instruction to the computer by means of the display and pen input part
1021
of the second terminal apparatus, this instruction information is transmitted from the wireless communication part
1023
. This instruction information is inputted to the wireless communication part
1012
of the first terminal apparatus
1001
and is transmitted to the CPU
1011
. The CPU
1011
inputs the instruction information and processes information according to the instruction information.
The user generally utilizes only the first terminal apparatus
1001
and the second terminal apparatus
1002
. The user can move about freely while carrying the second terminal apparatus
1002
, which is light and has no connection lines.
The user can also construct and utilize a computer system comprising the first terminal apparatus
1001
, the docking station
1004
, the keyboard
1005
and the display part
1006
by connecting the docking station
1004
to the first terminal apparatus
1001
and by connecting the keyboard
1005
and the display part
1006
to the docking station
1004
.
The conventional PC
1003
can incorporate a wireless communication part
1031
, which is an option. The video information generated by the CPU of the PC
1003
is transmitted from the wireless communication part
1031
. The wireless communication part
1023
of the second terminal apparatus
1002
receives the video information and transmits it to the display and pen input part
1021
. The display and pen input part
1021
displays the inputted video information.
When the user inputs, with the pen
1022
, an instruction to the computer by means of the display and pen input part
1021
of the second terminal apparatus, this instruction information is transmitted from the wireless communication part
1023
. The wireless communication part
1031
, which is incorporated in the conventional PC
1003
, inputs this instruction information and transmits it to the CPU. The CPU of the conventional PC
1003
inputs the instruction information and processes information according to the instruction information.
In this manner, the user can utilize a conventional PC as the first terminal apparatus
1001
.
FIG. 11
is a block diagram of a conventional computer which has a first terminal apparatus and a second terminal apparatus (primarily shows a transmission apparatus for video information and a transmission system for video information included in the computer). The conventional computer of
FIG. 11
includes a transmission apparatus for video information which transmits video information from the first terminal apparatus to the second terminal apparatus.
In
FIG. 11
, the first terminal apparatus is denoted as
1101
, the second terminal apparatus is denoted as
1102
, a display (display part) is denoted as
1003
and a wire for connecting the first terminal apparatus
1101
with the second terminal apparatus
1102
is denoted as
1104
.
The first terminal apparatus
1101
has a CPU
1111
, a video graphics control part
1113
, an LCD driving part
1115
(liquid crystal display driving part), a liquid crystal display
1116
and a communication board
1114
. The description of a ROM, a RAM or the like, which do not directly relate to the present invention, is omitted though they are indispensable to a computer.
The CPU
1111
, the video graphics control part
1113
and the communication board
1114
are connected to each other via a PCI bus
1112
.
The video graphics control part
1113
has a CPU
1121
, an input/output part
1122
, a RAM
1123
, a VRAM
1124
, a write in/read out address register
1125
, a read out address register
1126
, a clock generator
1127
and a parallel/serial conversion part
1128
.
The CPU
1121
, the input/output part
1122
, the RAM
1123
, the VRAM
1124
, the write in/read out address register
1125
and the like are connected to each other via an internal bus
1129
.
The CPU
1111
transmits an instruction described in a software language (for example, DirectX (registered trademark of Microsoft Corporation)) for changing the video to the video graphics control part
1113
and the communication board
1114
via the PCI bus
1112
.
The input/output part
1122
of the video graphics control part
1113
transmits the inputted instruction described in a software language for changing the video to the CPU
1121
via the internal bus
1129
.
The CPU
1121
converts an instruction described in a software language (program arranged on an Application Programming Interface of OS of the computer) for changing the video into level information (for example, information concerning the value to which the value of any address of the VRAM is changed) of each pixel at a hardware level by utilizing a video information decoder
1141
. The RAM
1123
is a scratch region at the time when level information of each pixel is generated by utilizing the video information decoder
1141
. The VRAM
1124
is a dual port RAM for video display which has a port which can write in or read out by randomly accessing an arbitrary address (an address is designated by the write in/read out address register
1125
) and a port which can read out data of each address at a high rate and in a constant order (an address is designated by the read out address register
1126
). The level information of each pixel (level information of each of the sub-pixels RGB), attribute data and the like are stored in the VRAM
1124
.
The CPU
1121
and the like set an address in the write in/read out address register
1125
. Information is written in to this address through the internal bus
1129
and information is read out from this address through the internal bus
1129
.
The clock generator
1127
sets a read out address register
1126
. The set value of the address register
1126
is generally incremented at an extremely high rate. The information of the address designated by the address register
1126
is read out and forwarded to the parallel/serial conversion part
1128
. The parallel/serial conversion part
1128
converts the inputted information of each address (level information of each pixel) into serial data, which are outputted.
The output signal of the parallel/serial conversio
Kobayashi Hisakazu
Masuno Takashi
Akin Gump Strauss Hauer & Feld L.L.P.
Johnson Timothy M.
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