Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2003-02-11
2004-02-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185110
Reexamination Certificate
active
06687154
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to digital memory devices and, more particularly, to a highly-integrated, Flash memory and mask ROM array architecture.
(2) Description of the Prior Art
In many electronic applications, it is desirable to combine more than one type of memory on one chip to reduce the cost and to increase the performance. One of the most popular and widely used single-chip combinations is flash memory and ROM.
Referring now to
FIG. 1A
, a conventional architecture for a memory card with security function is shown. This type of memory card is a passive device. Data may be stored in the card and may be changed during a card read operation. Passive memory cards of this type are widely used for phone card, health insurance card, vending machine card, and car parking card applications. The memory card contains address and security logic
11
to insure secure data exchange, a ROM array
12
to store the security code and data, a Flash or EEPROM array
13
to store the variable data, and I/O logic
14
to perform the data interface.
Referring now to
FIG. 1B
, a conventional architecture for a microprocessor card, or ‘smart card’, is shown. A smart card typically contains an 8-bit to 32-bit MCU or central processing unit (CPU)
15
. Some smart cards contain digital signal processors (DSP) to do data storage, management, processing and user interface. The smart card can support one application or multiple applications according to the stored application program run on the MCU. Typically, the smart card software can be freely programmed. Some smart cards even provide an open application program interface to allow new program code to be downloaded. Therefore, the functionality of the smart card is not restricted. One example for the smart card application is the mobile phone card.
The smart card shown contains a CPU
15
to perform the data processing, a RAM array
10
to act as working memory for temporary data storage, a ROM array
12
for storing the operating system, a Flash or EEPROM array
13
to store the variable data, and I/O logic
14
to perform the data interface.
Some of these prior art applications use a flash memory and a ROM on one chip. However, the Flash and ROM arrays are implemented as two discrete arrays. A large amount of chip area is wasted because array access circuitry, signal bus, and data bus must be duplicated for each type of memory array. Thus, it is highly desirable to further integrate the Flash memory and the ROM into one array. This will result in a highly cost-effective system on chip (SOC).
Flash memory is widely used, especially for portable applications, because of its non-volatility and in-system reprogrammability. The basic Flash memory cell structure consists of a control gate, a floating gate, source, and drain. The source and drain are two heavily doped regions on a silicon substrate. A channel exists for electrons to flow from drain to source. The floating gate is located between the control gate and channel. The floating gate is isolated by a thin-tunnel oxide layer and by a dielectric layer. The thin tunnel oxide layer exists between the floating gate and channel. The dielectric material is located between the control and floating gates. The insulators around the floating gate enable electrons to be trapped.
By biasing the control gate, drain, and source with proper voltages, electrons can move in to or out of the floating gate through the tunnel oxide layer. If the electrons move between the channel and floating gate, this operation is considered a ‘channel-operation.’ An ‘edge-operation’, in contrast, is defined as electrons moving between the floating gate and the edge of the source or drain.
Increasing the number of electrons raises the cell's threshold voltage. The threshold voltage is the voltage needed to allow current to flow. The threshold voltage shifts depending on the amount of charged trapped in the floating gate. Therefore, injecting or removing electrons can be used as means to store data. Two different operations are used for changing the Flash memory cell threshold voltage. The erase operation is applied to a large number of cells called a ‘block’. Erasing will collectively change the cell threshold voltage to a high or a low threshold voltage. The program operation is performed on a smaller number of cells called a ‘page’. Programming changes each cell threshold voltage depending on the desired data. Various mechanisms and technologies are used for erasing and programming different types of Flash memories. In this present invention, the well-known, Fowler-Nordheim (F-N) tunneling mechanism is chosen as an example.
A memory array consists of a plurality of cells arranged in columns and rows. The control gates of the cells in each row are connected to form word lines. The sources and drains of the cells in a column are connected to form source and bit lines. A cell can be read, erased, and programmed in this array by applying proper bias conditions to the word lines and bit lines.
Referring now to
FIG. 2
, a prior art, NOR-type Flash memory array is illustrated. A small array is shown comprising two word lines
20
a
and
20
b,
and two bit lines
21
and
22
, and four memory cells M
21
a,
M
21
b,
M
22
a,
and M
22
b.
This type of memory array is suitable for high-speed applications because the bit lines
21
and
22
can be formed using a metal layer having a very short bit line, delay time. Therefore, this type of Flash array is suitable for use in embedded, smart card, or SOC applications as mentioned above.
However, this prior art has several significant disadvantages in embedded applications. Each cell structure M
21
a
contains one transistor and is called a ‘1T cell.’ This type of 1T cell is susceptible to an over-erase condition. In an over-erase condition, the threshold voltage (V
th
) of a Flash transistor becomes negative during the erase operation. An over-erased cell will not completely turn OFF when the control gate bias is in the OFF state. The presence of an over-erased Flash cell on a bit line will cause bit line leakage current. Read errors will occur due to this leakage.
To prevent over-erase problems, an additional operation must be performed following the erase operation. A correction operation is performed in order to eliminate the over-erased cells. The correction operation is equivalent to a soft-program operation to increase the V
th
of over-erased cells back to a positive range. This correction must be performed on a bit-by-bit basis to prevent overshooting the desired V
th
range. Therefore, the correction operation is complex and requires a complicated state machine. In addition, the correction operation significantly slows the re-write cycle of the Flash memory cells and is, therefore, not suitable for the above-described, embedded applications.
An additional problem with the 1T cells of the prior is handling high voltage. During programming, a high voltage signal must be applied to the bit lines. This high voltage will be coupled to the floating gate by the junction-floating gate overlapping area. This cell will turn ON slightly and create bit line current leakage. Each bit line contains a huge number of cells, and, in page-programming mode, a large number of bit lines will be programmed together. Therefore, the lump sum of leakage currents can be substantial. The high voltage signal applied to the bit lines is generated by on-chip, charge pump circuitry. The charge pump circuit is limited in current capability and may not be able to sustain the large leakage current during programming. If the leakage current is too large, the high voltage signal will drop in voltage and cause very slow programming times.
Referring now to
FIG. 3
, another prior art discloses a two transistor (2T) structure to eliminate the over-erase problem. The 2T cell M
31
contains a floating-gate, Flash cell M
31
a
and a select transistor M
31
b.
The select transistor M
31
b
is an enhancement NMOS, having a positive V
th
of, for example, +0.7V.
Hsu Fu-Chang
Lee Peter W.
Ackerman Stephen B.
Aplus Flash Technology Inc.
Le Vu A.
Saile George O.
Schnabel Douglas R.
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