System for monitoring and capturing bus data in a computer

Details System for monitoring and capturing bus data in a computer System for monitoring and capturing bus data in a computer

1988-03-24

1990-09-25

Zache, Raulfe B.

Boots, shoes, and leggings

364267, 36426791, 3642327, 364240, 3642401, 364238, 364243, 364252, G06F 1300

Patent

active

049597728

ABSTRACT:
A system for troubleshooting or debugging the various modules of a digital computer which are connected to the ports of a common system bus. A control unit transmits serial function and data codes to a serial bus link gate array whose parallel outputs are further processed to generate steering and clock commands. A first set of bus interface multiplexers are connected to each of the lines of the address, data and control fields of the system bus. A second set of multiplexers cause information represented by digital signals on selected ones of the lines in selected ones of the fields to be stored in a plurality of RAMs in response to the steering commands. A trigger logic is provided for selectively starting and stopping different clock signals in response to the clock commands. Information can be stored in the RAMs continuously until the RAMs are full, until a specified smaller amount of information has been stored in the RAMs, or until a specified event occurs, in response to predetermined ones of the function and data codes. The control unit can retrieve and organize the information captured in the RAMs for display to enable a system operator in locating faults in the computer.

REFERENCES:
patent: 3999053 (1976-12-01), Dalmasso
patent: 4166290 (1979-08-01), Furtman et al.
patent: 4308615 (1981-12-01), Koegel et al.
patent: 4392208 (1983-07-01), Burrows et al.
patent: 4459656 (1984-07-01), Wilder, Jr.
patent: 4636941 (1987-01-01), Suko
patent: 4639917 (1987-01-01), Furuta

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