Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-02-04
2004-08-17
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S230030
Reexamination Certificate
active
06778439
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device with an MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.
2. Description of the Background Art
An MONOS type flash EEPROM (Electrically Erasable Programmable Read Only Memory) is known as one type of flash EEPROMs which are nonvolatile semiconductor memory devices. In the MONOS type memory cell, an ONO (SiO
2
—Si
3
N
4
—SiO
2
) film exists between a control gate and the channel. In this memory cell, two bit data can be stored depending on whether or not electrons are trapped in each of the source side portion and the drain side portion of the Si
3
N
4
layer. In addition, this memory cell has a simpler manufacturing process and is less expensive compared to a memory cell having a floating gate. Such a memory cell is disclosed, for example, in U.S. Pat. No. 6,011,725.
Furthermore, U.S. Pat. No. 4,173,791 discloses a configuration of an MNOS (Metal Nitride Oxide Semiconductor) type flash EEPROM memory array.
In this memory array, adjacent two memory cells in the same row share a bit line. This is because a direction of a current flowing through the channel need to be reversed between a reading operation and a writing operation, and because two bit data need to be stored in one memory cell.
However, when two bit data are to be stored in the MONOS type memory cell, a reduction in distance between the source side portion and the drain side portion of the Si
3
N
4
layer is difficult to achieve, and consequently, the layout area becomes larger.
Furthermore, in the above-described memory array configuration, the following problems arise. That is, compared to a conventional memory array configuration in which a bit line is provided to each column, a voltage control of the bit line becomes more complicated, a bit line control circuit configuration increases in complexity, and a time period for design takes longer.
U.S. Pat. No. 4,173,791 mentioned above discloses an EEPROM in which a conventional memory array is configured of MNOS type memory cells trapping electrons in a gate insulator film. Different from the MONOS type memory cell, however, the MNOS type memory cell has no oxide film between a gate electrode and a nitride film. Accordingly, electrons trapped in the nitride film tend to be easily leaked into the gate electrode. Therefore, a data retention capability of the memory cell is low.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a nonvolatile semiconductor memory device with a simple manufacturing process, a high data retention capability, a small layout area, and a simplified configuration.
A nonvolatile semiconductor memory device in accordance with the present invention includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each including a semiconductor substrate, a first insulator layer, a charge trapping layer, a second insulator layer, and a gate electrode successively stacked on a surface of the semiconductor substrate, and the source and the drain respectively formed on the surface of the semiconductor substrate at one side and the other side of the gate electrode. The nonvolatile semiconductor memory device further includes a plurality of word lines respectively provided corresponding to the plurality of rows, each being connected to the gate electrode of each corresponding memory cell. The nonvolatile semiconductor memory device further includes a plurality of bit lines respectively provided corresponding to the plurality of columns, each being connected to the drain of each corresponding memory cell. The nonvolatile semiconductor memory device further includes a source line commonly connected to the sources of the plurality of memory cells, and a read circuit selecting any of the plurality of memory cells in accordance with an address signal and reading a data signal of the selected memory cell. The read circuit includes a first word line drive circuit applying a predetermined first potential to a word line corresponding to the selected memory cell while applying a ground potential to other word lines, a first bit line drive circuit applying a predetermined second potential to a bit line corresponding to the selected memory cell while applying the ground potential to other bit lines, a first source line drive circuit applying the ground potential to a source line, and a current detection circuit detecting whether or not a current flows in the bit line corresponding to the selected memory cell and outputting the data signal at a level corresponding to a detection result. Accordingly, since the MONOS type memory cell is utilized, a simplification of the manufacturing process and an improvement in the data retention capability can be achieved. In addition, the MONOS type memory cell is utilized to make a conventional memory array and it is used as a one bit/cell-memory cell. Accordingly, a reduction in the layout area and simplification of the configuration are possible. Furthermore, since the read circuit is composed of the first word line drive circuit, the first bit line drive circuit, the first source line drive circuit, and the current detection circuit, reading the data signal can be performed easily and accurately.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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patent: 4173766 (1979-11-01), Hays
patent: 4173791 (1979-11-01), Bell
patent: 5768192 (1998-06-01), Eitan
patent: 6011725 (2000-01-01), Eitan
patent: 6314044 (2001-11-01), Sasaki et al.
patent: 5-136376 (1993-06-01), None
Boaz Eitan et al., “Can NROM, a 2 bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”. The 1999 International Conference on Solid State Devices and Materials, Tokyo, Japan, Sep. 21-24, 1999, pp. 522-524.
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Burns Doane Swecker & Mathis L.L.P.
Tran M.
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