Static random access memory cell and method

Details Static random access memory cell and method Static random access memory cell and method

2001-12-20

2004-02-03

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S154000

Reexamination Certificate

active

06687145

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to digital memory systems and more particularly to an improved static random access memory cell and method.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers and other components of an integrated circuit. One type of memory array is a static random access memory (SRAM) in which memory cells are continuously available for reading and writing data. As technology improves, SRAM cells and other components are fabricated at smaller sizes.
For maximum performance in an SRAM cell, drive transistors within the cell are typically designed with a minimum gate length. However, in high performance transistors, threshold voltage varies strongly as a function of gate length. Thus, as gate length is reduced, the transistor's threshold voltage decreases, resulting in a deterioration in noise margin and leakage current for the SRAM cell.
The primary design factor controlling the noise margin of an SRAM cell is the ratio of the strength of the drive transistor to the strength of the pass transistor. The weaker the pass transistor relative to the drive transistor, the greater the noise margin. The greater the variability of the elements of an SRAM cell, the greater the required noise margin. In minimum area SRAM cells, the drive transistor is generally near minimum width.
Thus, to reduce the pass transistor strength relative to the drive transistor strength, the gate length of the pass transistor is made longer than the gate length of the pass transistor. For larger cells, the relative strengths of the driver and pass transistors may be adjusted by having the drive transistor wider than the pass transistor. Even when the drive transistor is made wider than the pass transistor, the pass transistor gate length may be made longer than the driver transistor gate length to reduce leakage to the bit line. The drive transistor gate length is generally made equal to the minimum gate length for the technology, both to improve the ratio of the drive transistor strength to pass transistor strength and to increase read current for a given SRAM cell area.
The read current of an SRAM cell is a primary performance characteristic of an SRAM cell. The read current is limited by both the drive transistor and the pass transistor but the pass transistor has a greater influence. Thus, weakening the pass transistor to improve noise margin decreases the performance of the SRAM cell. Nevertheless, adequate noise margin must be maintained to allow for variability of the SRAM cell components. As technology is scaled, variability tends to increase as a percentage. Thus, as SRAM cells are scaled, the typical procedure is to scale the gate length of the drive transistor as allowed by the technology and to adjust the gate length of the pass transistor to obtain adequate noise margin at minimum area, with some sacrifice of performance.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved static random access memory (SRAM) cell and method are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides an SRAM cell with a drive transistor having a gate length corresponding to a threshold voltage that does not vary strongly with gate length, resulting in increased noise margin and reduced leakage current for the SRAM cell without a substantial decrease in performance.
In one embodiment of the present invention, a method is provided for forming a scaled static random access memory (SRAM) cell based on an initial SRAM cell for implementation in a technology scaled from an initial technology. The SRAM cells comprise a plurality of transistors. The method comprises determining a reduction in a minimum gate length for the scaled transistors as compared to a minimum gate length for the initial transistors. The method also comprises forming a scaled drive transistor comprising a gate having a gate length reduced as compared to a gate length for an initial drive transistor. The scaled gate length is reduced by less than the determined reduction in the minimum gate length.
In another embodiment of the present invention, an integrated circuit is provided. The integrated circuit comprises a periphery comprising a plurality of transistors. Each transistor comprises a gate having a specified gate length. The integrated circuit also comprises an SRAM cell comprising a plurality of transistors. The transistors comprise a drive transistor. The drive transistor comprises a gate having a gate length greater than the specified gate length.
In yet another embodiment of the present invention, a method is provided for forming a scaled SRAM cell. The method comprises scaling a pass transistor comprising a gate from a first gate length to a second gate length. The second gate length is a specified percentage of the first gate length. The method also includes scaling a drive transistor comprising a gate from a first gate length to a second gate length. The second gate length is a specified percentage of the first gate length. The specified percentage for the drive transistor is greater than the specified percentage for the pass transistor.
Technical advantages of the present invention include providing an improved SRAM cell. In a particular embodiment, the SRAM cell has a drive transistor with a gate length that is increased beyond the minimum gate length such that the threshold voltage is no longer a strong function of gate length. As a result, the threshold voltage is increased, resulting in the worst case noise margin increasing and leakage current decreasing. However, a pass transistor for the SRAM cell has a gate length that is not increased in proportion to the increase in the drive transistor gate length. Accordingly, the SRAM cell has an improved noise margin and leakage current without a substantial decrease in speed.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.


REFERENCES:
patent: 5903036 (1999-05-01), Onozawa
patent: 6417032 (2002-07-01), Liaw

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